This hardware manual describes the PCL-069 System on Module, referred to as phyCORE®-i.MX 8M Mini, and the PBA-C-15, referred to as phyBOARD®-Polis. This manual also specifies the phyCORE-i.MX 8M Mini and phyBOARD-Polis' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Mini microcontrollers can be found in the i.MX 8M Mini Microcontroller Data Sheet/Reference Manual.

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secondary	Design Considerations
primary	Information on this Manual

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

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http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

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Ordering Information

The part numbering of the phyCORE has the following structure:

PCL-069 Ordering Information Image Modified

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Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

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Note

title	Note

Assembly Options include a choice of Controller, RAM (Size/Type), Size of NAND Flash, interfaces available, vanishing, temperature range, as well as other features. Please contact our sales team to get more information on the ordering options available.

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Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Mini

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Image Modified

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

Warning

title	Warning

PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be unpacked, handled, or operated in environments in which sufficient precautionary measures have been taken in with respect to ESD - dangers. Only appropriately trained personnel such as qualified electricians, technicians, and engineers should handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in with respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Tip

title	Tip

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as the implementation of the products into target systems.

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Product Change Management and Information Regarding Parts Populated on the SOM / SBC
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PCM
PCM

With the purchase of a PHYTEC SOM / SBC you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

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Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
Offer long-term frame contracts to customers.

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Avoid impacts on product functionality by choosing equivalent replacement parts.
Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

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PHYTEC Documentation

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PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

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Tip

title	Tip

The BSP delivered with the phyCORE-i.MX 8M Mini includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at register level is not necessary in most cases. For this reason, this manual contains no detailed description of the controller's registers or information relevant to software development. Please refer to the NXP i.MX 8M Mini Reference Manual, if such information is needed to connect customer-designed applications.

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Conventions

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The conventions used in this manual are as follows:

Signals that are preceded by an "n", "/", or “#”character “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low, or are driving low.
A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
The hex - numbers given for addresses of I²C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g. given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device
Tables that describe jumper settings show the default position in bold, blue text.

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Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

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title	Signal Types

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Signal Type	Description	Abbreviation
Power	Supply voltage input	PWR_I
Ref-Voltage	Reference voltage output	REF_O
Input	Digital input	I
Input-Pullup	Input with pull up	I-PU
Output	Digital output	O
IO	Bidirectional input/output	I/O
OC-Bidir	Open collector input/output with pull up	OC-BI
OC-Output	Open collector output without pull up requires an external pull up	OC
OD-Bidir PU	Open-drain input/output with pull up	OD-BI
OD-Output	Open-drain output without pull up requires an external pull up	OD
OD-Output-Pullup	Open-drain output with pull up	OD-PU
5V Input PD	5 V tolerant input with pull-down	5V_PD
USB IO	Differential line pairs 90 Ohm USB level bidirectional input/output	USB_I/O
ETHERNET Input	Differential line pairs 100 Ohm Ethernet level input	ETH_I
ETHERNET Output	Differential line pairs 100 Ohm Ethernet level output	ETH_O
ETHERNET IO	Differential line pairs 100 Ohm Ethernet level bidirectional input/output	ETH_I/O
PCIe Input	Differential line pairs 85 Ohm PCIe level input	PCIe_I
PCIe Output	Differential line pairs 85 Ohm PCIe level output	PCIe_O
MIPI CSI-2 Input	Differential line pairs 100 Ohm MIPI CSI‑2 level input	CSI2_I
MIPI DSI-2 Output	Differential line pairs 100 Ohm MIPI DSI-2 level input	DSI2_O
CAN FD IO	Differential line pairs 120 Ohm CAN FD level bidirectional input/output	CAN_I/O
CAN FD IO	Differential line pairs 120 Ohm CAN FD level bidirectional input/output	CAN_I/O
Wireless	Wireless signal input/output	WL_I/O

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Abbreviations and Acronyms
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Abbreviations and Acronyms
Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate any unfamiliar terms used in this document.

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Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 37 % of all connector pinson the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Mini is a sub-miniature (37 mm x 40 mm) soldered System on Module populated with the NXP® Semiconductor i.MX 8M Mini microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to a 1,27mm pitch BGA Ball. Each signal ball has an associated GND pin which ensures the GND reference for each signal. The ball packages are placed in lines. There is enough space between lines to ensure the possibility of easy routing out of the package. Signal balls for a high-speed signal like HDMI are placed on the outer lines, making it easy to route to the top layer of the carrier board. The SOM is designed to support carrier boards with as little few as 6 layers to reduce PCB costs. For proper EMC characteristics, it is necessary to place the processor caps directly under the SOM. This required a hole in the carrier board.

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Mini. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Mini.

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phyCORE‑i.MX 8M Mini Features

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The phyCORE‑i.MX 8M Mini offers the following features:
Insert-ready, sub-miniature (37 mm x 40 mm) System on Module (SOM) sub-assembly in low EMI design, achieved through advanced SMD technology
Mounted using BGA Technology
Populated with the NXP® Semiconductor i.MX 8M Mini microcontroller (BGA486 packaging)
1.6 GHz core clock frequency (up to 1.8 GHz)
Boot from different memory devices (eMMC standard)
Single supply voltage of +3.3 V with onboard power management
All controller-required supplies are generated onboard
Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
2 GB (up to 4 GB)
Single cite
citeID 1
The maximum memory size listed as of the printing of this manual.
Please contact PHYTEC for more information about additional or new module configurations available.
) LPDDR4 RAM
4 GB (up to 32 GB
Single cite short
citeID 1
) onboard eMMC
4 kB
Single cite short
citeID 1
I²C EEPROM
2x High-Speed USB 2.0 OTG interfaces
1x 10/100/1000 MBit Ethernet interface (if Ethernet transceiver is mounted)
Single cite
citeID 2
Please refer to the order options described in the L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head
or contact PHYTEC for more information about additional module configurations.

One RGMII interface at TTL level (if Ethernet transceiver is not mounted)
Single cite short
citeID 2
Three I²C interfaces
Two SPI interfaces
One PCIe interface
Four UART interfaces
Four PWM outputs
One LVDS interface (if MIPI-DSI to LVDS converter is mounted)
Single cite short
citeID 2
One MIPI DSI interface (if MIPI-DSI to LVDS converter is not mounted)
Single cite short
citeID 2
One MIPI CSI camera interface
One 4-Bit SD-Card interface
One 8-Bit SDIO interface
SAI audio interface
Internal RTC
Available for different temperature grades (L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head)
Cite summary
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phyCORE-i.MX 8M Mini Block Diagram
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phyCORE-i.MX8M Mini Block Diagram
phyCORE-i.MX8M Mini Block Diagram

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title	phyCORE-i.MX 8M Mini Block Diagram

phyCORE-i.MX 8M Mini Block Diagram

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phyCORE-i.MX 8M Mini Component Placement
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phyCORE-i.MX 8M Mini Component Placement
phyCORE-i.MX 8M Mini Component Placement

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title	phyCORE-i.MX 8M Mini Component Placement (Top)

phyCORE-i.MX 8M Mini Component Placement (Top)

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title	phyCORE-i.MX 8M Mini Component Placement (Bottom)

phyCORE-i.MX 8M Mini Component Placement (Bottom)

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phyCORE-i.MX 8M Mini Minimal Operating Requirements
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phyCORE-i.MX 8M Mini Minimal Operating Requirements
phyCORE-i.MX 8M Mini Minimal Operating Requirements

Warning

We recommend connecting all available VDD_3V3 input pins to the power supply system on a custom carrier board housing the phyCORE-i.MX 8M Mini and, at minimum, the matching number of GND pins neighboring the VDD_3V3 input pins. In addition, proper implementation of the phyCORE-i.MX 8M Mini module into a target application also requires connecting all GND pins.
Refer to L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head for more information.

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Pin Description
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Anchor
Pin Description
Pin Description

Warning

Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user 's responsibility to must take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

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Tip

title	Tips

Most of the controller pins have multiple multiplexed functions. As most of these pins are connected directly to the phyCORE-Connector, the alternative functions are available by using the i.MX 8M Mini's pin muxing options. Signal names and descriptions in the accompanying table, however, are in regard to the specification of the phyCORE‑i.MX 8M Mini and the functions defined. Please refer to the i.MX 8M Reference Manual or the schematic to get to know about alternative functions. In order to utilize a specific pin's alternative function, the corresponding registers must be configured within the appropriate driver of the BSP.
In case a design requires specific logic levels at it's its signals, special attention has to be paid to the settings of i.MX 8M Mini's internal pull resistors. It is good design practice to never rely on the SoC-internal pull resistors.
The following tables describe the full set of signals available at the phyCORE‑Connector according to the phyCORE-i.MX 8M Mini specification. However, the availability of some interfaces is order-specific (e.g. Camera_0). Thus, some signals might not be available on your module.
As the phyCORE-i.MX 8M Mini is delivered with the carrier board phyBOARD‑Polis, the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. If so, information on the differences from the pinout given in the following tables can be found in the carrier board's documentation.

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Note

title	Errata information

Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR050080: IO: Degradation of internal IO pullup/pulldown current capability for IO’s continuously driven in a 3.3V operating mode

It is good design practice to never rely on the SoC-internal pull resistors.

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primary	Unused Signals

Unused Signals
Anchor
Pin Description
Pin Description

It is recommended to handle unused signals according to the table below:

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The phyCORE‑i.MX 8M Mini operates off of a single power supply voltage. The following sections discuss the primary power pins on the phyCORE-i.MX 8M Mini Connector X1 in detail.

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secondary	Primary System Power (VDD_3V3)
primary	Power

Primary System Power (VDD_3V3)
Anchor
Primary System Power (VDD_3V3)
Primary System Power (VDD_3V3)

The phyCORE‑i.MX 8M Mini operates with a single primary voltage supply. Onboard switching and low dropout regulators generate the 2.5 V, 1.8 V, 1.2 V, 1.1 V, 0.9 V, and 0.8 V voltage rails required by the i.MX 8M Mini CPU and onboard components from the input voltage VDD_3V3.

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Warning

title	Warning

As a general design rule, PHYTEC recommends connecting all GND pins neighboring signals which are being used in the application circuitry. For maximum EMI performance, all GND pins should be connected to a solid ground plane.

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Power Management IC (PMIC)(U3)

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Power Management IC (PMIC)(U3)
Power Management IC (PMIC)(U3)

The phyCORE-i.MX 8M Mini provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head figure presents a graphical depiction of the powering scheme. The PMIC supports many functions like on-chip RTC and different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Mini via the onboard I²C bus (I2C1) (L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head). The I²C address of the PMIC is 0x08.

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Power Domains

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Power Domains
Power Domains
Anchor
phyCORE-i.MX 8M Mini Powering Scheme
phyCORE-i.MX 8M Mini Powering Scheme

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title	phyCORE-i.MX 8M Mini Powering Scheme

i.MX 8M Mini Power Scheme Block Diagram

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title	Internally Generated Voltages

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VDD_SOC_VDDA_PHY_0P8	i.MX 8M Mini SOC logic and PHY supply (VDD_SOC1-12, VDD_ARM_PLL_0P8, VDD_ANA_0P8_1-2, VDD_PCI_0P8, VDD_USB_0P8) (0.8 V)
VDD_GPU_DRAM	i.MX 8M Mini 3D GPU and DRAM supply (VDD_GPU1-5, VDD_DRAM1-6, VDD_DRAM_PLL_0P8) (0.8/0.9 V)
VDD_VPU	i.MX 8M Mini MIPI PLL, logic (VDD_MIPI_0P9) (0.9 V)
VDD_MIPI_0P9	i.MX 8M Mini MIPI PLL, logic (VDD_MIPI_0P9) (0.9 V)
VDD_ARM	i.MX 8M Mini Mini ARM supply (VDD_ARM1-14) (0.8/0.9 V)
NVCC_DRAM_1P1V	DRAM supply (NVCC_DRAM1-13) (1.1 V)
VDD_1V8	i.MX 8M Mini general 1.8 V supply (VDD_ARM_PLL_1P8, VDD_ANA0_1P8_1-2, VDD_ANA1_1P8_1-2, VDD_DRAM_PLL_1P8, VDD_USB_1P8, VDD_MIPI_1P8, VDD_PCI_1P8) (1.8)
NVCC_SD2	i.MX 8M Mini SDIO2 supply (NVCC_SD2) (1.8/3.3 V)
VDDA_1V8	i.MX 8M Mini 1.8 V analog supply (VCC_24M_XTAL_1P8. PVCC0_1P8, VCC2_1P8, NVCC_ENET, NVCC_NAND, NVCC_CLK) (1.8 V)
NVCC_SNVS_1P8	i.MX 8M Mini SNVS GPIO driver supply /NVCC_SNVS_1P8) (1.8 V)
VCC_ENET_2V5	i.MX 8M Mini Ethernet PHY supply (U4) (2.5 V)
NVCC_SD1	i.MX 8M Mini SDIO1 supply (NVCC_SD1) (3.3 V PHYTEC default setting, 1.8 V possible through software adjustment)
VDD_3V3_S	i.MX 8M Mini general 3.3 V supply (NVCC_JTAG, NVCC_SAI1-3, NVCC_SAI5, NVCC_GPIO1, NVCC_I2C, NVCC_UART, NVCC_ECSPI, VCC_USB_3P3) (3.3 V)

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External Logic Supply Voltage

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External Logig Supply Voltage
External Logig Supply Voltage

The voltage level of the phyCORE’s logic circuitry is VDD_3V3_S (3.3 V) which is derived from the SOM main input voltage, VDD_3V3. In order to follow the mandatory power-up and power-down sequencing for the i.MX 8M Mini, external devices have to be supplied by the I/O supply voltage VDD_3V3_S which is brought out at pin E14 of the phyCORE-Connector. The use of VDD_3V3_S ensures that external components are only supplied when the supply voltages of the i.MX 8M Mini are stable.

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Tip

title	Tip

If used to control or supply bus switches on the phyCORE side, VDD_3V3_S separates the supply voltages generated on the phyCORE‑i.MX 8M Mini and the supply voltages used on the carrier board/custom application. This way, voltages at the IO pins of the phyCORE-i.MX 8M Mini which are sourced from the supply voltage of peripheral devices attached to the SOM are avoided.

These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M Mini are supposed to be powered while the phyCORE‑i.MX 8M Mini is in suspend mode or turned off. The bus switches can be supplied by VDD_3V3_S on the phyCORE side, or the bus switches' output enabled to the SOM can be controlled by X_PGOOD to prevent these voltages from occurring.

The use of level shifters supplied with VDD_3V3_S allows the signals to be converted according to the needs of the custom target hardware. Alternatively, signals can be connected to an open drain circuitry with a pull-up resistor attached to VDD_3V3_S.

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Backup Power (VBAT)
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Backup Power
Backup Power

At pin A79 (Signal VBAT) of the phyCORE-i.MX 8M Mini, a secondary 3.3 V voltage source may be attached to the SOM. The PMIC (U3) will use this secondary source to generate NVCC_SNVS_1P8 in case VDD_3V3 falls below a value of approx. 2.8 V.

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On-Board RTC and RTC Backup Power (VRTC)
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Backup Power

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Backup Power

At pin A102 (Signal VRTC) of the phyCORE-i.MX 8M Mini, a secondary voltage source may be attached to the SOM in order to buffer the onboard RTC U12, while the SOM input voltage is not present. This manual describes only one of the available RTC active power states, which is used in conjunction with the phyBOARD-POLIS and the phyCORE-i.MX 8M Mini. The RTC RV-3028-C7 will enter its backup mode as soon as it detects the voltage level at Pin VRTC to be higher than the SOM input voltage VDD_3V3.

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Warning

title	Warning

In its backup power state, the RTC will cease to communicate over I2C1 if the voltage level at the Pin VRTC is higher than the SOM input voltage VDD_3V3. In order to avoid unnecessary problems, the recommended voltage difference between VDD_3V3 and VRTC is approx. 300 mV.

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primary	Reset

Reset
Anchor
Reset
Reset

Pin C43 on the phyCORE-Connector is designated as an open-drain reset input with a pull-up resistor, that triggers a hard reset of the module. The external reset signal is connected to the enable signal of the voltage supervisor U41, which triggers a watchdog event in the PMIC resulting in a hard reset of the module. For debouncing purposes, the U41 delays the signal by 8,804 ms.

For PCB version versions 1518.0, 1518.1a and 1518.2 additional precautions have to be taken regarding the undervoltage detection of the phyCORE-i.MX 8M Mini. X_nPOR_IN must be held on a logical low level, as long as VDD_3V3 is below 3.135 V. If this is not considered in the design of a baseboard, there is a small chance , that the SoM could enter an unspecified mode of operation. PCB version 1518.3 and higher will not require this feature any longer, yet it is good engineering practice, to monitor all voltage rails at all times.

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System Boot Configuration
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System Boot Configuration System Boot Configuration

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System Boot

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Configuration

i.MX 8M Mini System Boot Settings

Most features of the i.MX 8M Mini microcontroller are configured and/or programmed during the initialization routine. Essential boot features however are latched into i.MX 8M Mini registers from pre-configured pull-resistors following power-on reset (POR_B) de-assertion.

The latched-in information includes:

Boot mode selection
Boot device selection
Detailed boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Mini after POR de-assertion. The ROM code detects the boot mode through pins X_BOOT_MODE0 and X_BOOT_MODE1, while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO pins (BOOT_CFGx[14:12]).

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Boot Mode Selection
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Boot Mode Selection
Boot Mode Selection

The i.MX 8M Mini boot mode is determined by the logical levels of the pins X_BOOT_MODE0 and X_BOOT_MODE1 approx. 31 µs after POR_B de-assertion. X_BOOT_MODE0 and X_BOOT_MODE1 are brought out at the phyCORE‑Connector pins C15 and C16. Possible settings and the resulting boot configuration of the i.MX 8M Mini are described in the following table:

Anchor

	phyCORE-i.MX 8M Mini Boot Modes
	phyCORE-i.MX 8M Mini Boot Modes

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In fuse boot and internal boot mode, the ROM code finds the bootloader in permanent memories, such as eMMC or SD-Cards, and executes it. The boot device selection and the required interface configuration are accomplished with the help of the eFUSEs and/or the corresponding GPIO input.

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Boot

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Device Selection and

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Configuration
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Anchor
Boot Device Selection and Configuration
Boot Device Selection and Configuration

In fuse boot and internal boot mode, the ROM code uses the BOOT_CFG pin states and eFUSEs to determine the boot device and its detailed configuration.

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title	phyCORE-Connector Boot Configuration Pins

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Configuration Pin	SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
BOOT_CFG[0]	A81	X_SAI1_RXD0/ BOOT_CFG[0]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 0 during reset SAI receive data 0 during runtime
BOOT_CFG[1]	A82	X_SAI1_RXD1/ BOOT_CFG[1]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 1 during reset SAI receive data 1 during runtime
BOOT_CFG[2]	A85	X_SAI1_RXD2/ BOOT_CFG[2]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 2 during reset SAI receive data 2 during runtime
BOOT_CFG[3]	A86	X_SAI1_RXD3/ BOOT_CFG[3]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 3 during reset SAI receive data 3 during runtime
BOOT_CFG[4]	A87	X_SAI1_RXD4/ BOOT_CFG[4]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 4 during reset SAI receive data 4 during runtime
BOOT_CFG[5]	A88	X_SAI1_RXD5/ BOOT_CFG[5]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 5 during reset SAI receive data 5 during runtime
BOOT_CFG[6]	A89	X_SAI1_RXD6/ BOOT_CFG[6]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 6 during reset SAI receive data 6 during runtime
BOOT_CFG[7]	A90	X_SAI1_RXD7/ BOOT_CFG[7]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 7 during reset SAI receive data 7 during runtime
BOOT_CFG[8]	A94	X_SAI1_TXD0/ BOOT_CFG[8]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 8 during reset SAI transmit data 0 during runtime
BOOT_CFG[9]	A95	X_SAI1_TXD1/ BOOT_CFG[9]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 9 during reset SAI transmit data 1 during runtime
BOOT_CFG[10]	A96	X_SAI1_TXD2/ BOOT_CFG[10]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 10 during reset SAI transmit data 2 during runtime
BOOT_CFG[11]	A97	X_SAI1_TXD3/ BOOT_CFG[11]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 11 during reset SAI transmit data 3 during runtime
BOOT_CFG[12]	A98	X_SAI1_TXD4/ BOOT_CFG[12]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 11 during reset SAI transmit data 4 during runtime
BOOT_CFG[13]	A99	X_SAI1_TXD5/ BOOT_CFG[13]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 13 during reset SAI transmit data 5 during runtime
BOOT_CFG[14]	A100	X_SAI1_TXD6/ BOOT_CFG[14]	VDD_3V3_S	3.3 V	I/O	Boot configuration pin 14 during reset SAI transmit data 6 during runtime

...

i.MX 8M Nano System Boot Settings
Anchor
System Boot Configuration
System Boot Configuration

The i.MX 8M Nano uses a boot process different from the i.MX 8M Mini. Boot devices with fixed configuration may be selected through the use of 6 Boot Mode pins, 2 of which are shared with the i.MX 8M Mini. The phyCORE-i.MX 8M Nano is pre-configured with the default Boot Mode setting eMMC boot.

...

Cite summary

showCitationLinks	false
local	true

...

LPDDR4-RAM (U2)
...
Anchor
LPDDR4-RAM (U2)
LPDDR4-RAM (U2)

The RAM memory of the phyCORE‑i.MX 8M Mini is comprised of one 32-bit wide bank with two 16-bit wide LPDDR4-RAM chips in one integrated circuit. The chips are connected to the DDR interface called the DDR Controller (DDRC) of the i.MX 8M Mini microcontroller.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Mini controller. Refer to the NXP i.MX 8M Mini Reference Manual for accessing and configuring these registers.

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QUAD SPI-NOR (U7)
Anchor
QUAD SPI-NOR (U7)
QUAD SPI-NOR (U7)

The Quad NOR flash memory at U7 is connected to the Flexible Serial Peripheral Interface A (FlexSPI A). The connected flash device uses the provided Chip Select 0 signal (QSPIA_SS0). The NOR flash device is powered by the 1.8 V supply voltage VDD_1V8. No further voltages are required to program the device.

...

For more information about the NOR Flash, please refer to the NXP i.MX 8M Mini Reference Manual.

...

eMMC Flash Memory (U21)

...

...
Anchor
eMMC Flash Memory (U21)
eMMC Flash Memory (U21)

The managed NAND (eMMC) flash device is powered by the supply voltages VDD_1V8 (1.8 V) and VDD_3V3_S (3.3 V). No further voltages are required for programming the device. The eMMC memory is connected to the SDIO3 interface of the i.MX 8M Mini. Any parts that are footprint (BGA153) and functionally compatible may be used with the phyCORE-i.MX 8M Mini.

For more information about the eMMC, please refer to the NXP i.MX 8M Mini Reference Manual.

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Scroll Indexterm

secondary	I2C EEPROM (U13)
primary	System Memory

I²C EEPROM (U13)
Anchor
I2C EEPROM (U13)
I2C EEPROM (U13)

The phyCORE‑i.MX 8M Mini is populated with a 4 kB I²C

...

Cite summary

showCitationLinks	false
local	true

...

EEPROM Write Control

...

...
Anchor
EEPROM Write Control
EEPROM Write Control

The Write Control (WC) signal of the EEPROM is permanently fixed to GND over resistor R106, so the EEPROM is not always write-protected.

...

The following sections detail each of these serial interfaces.

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SDIO Interfaces
...
Anchor
SDIO Interfaces
SDIO Interfaces

The SDIO interfaces are part of the ultra Secured Digital Host Controller and can be used to connect external SD-Cards, eMMC, or any other device requiring an SDIO interface (examples include WiFI, I/O expansion). The phyCORE‑i.MX 8M Mini features two SDIO interfaces (4 and 8-Bit). On the phyCORE‑i.MX 8M Mini, the interface signals extend from the controller's first and second Ultra Secured Digital Host Controller (uSDHC1/uSDHC2) to the phyCORE-Connector.

uSDHC2 provides dedicated card-detect, write-protect and power enable signals. For uSDHC2 to function a pull-up resistor (eg. 10k) from X_SD2_PWR_EN to the SOM input voltage VDD_3V3 is required. This enables the uSDHC2 interface by powering the corresponding domain in the i.MX 8M Mini. This feature may be used to limit access to the CPU through an openly available SD-Card slot, or for similar purposes.

uSDHC1 card-detect and write-protect functions may be implemented by using GPIOs of the i.MX 8M Mini. Refer to the NXP i.MX 8M Mini Reference Manual. For more information about SD-Cards, please refer to the manufacturer's user manual.

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Scroll Title

anchor	SDIO2 Interface Signal Locations
title	SDIO2 Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
C18	X_SD2_RESET_B	NVCC_SD2	1,8 V/ 3,3 V	O	SD2 reset output
C19	X_SD2_WP	NVCC_SD2	1,8 V/ 3,3 V	O	SD2 write-protect output
C20	X_SD2_CD_B	NVCC_SD2	1,8 V/ 3,3 V	O	SD2 card detect
C21	X_SD2_DATA1	NVCC_SD2	1,8 V/ 3,3 V	I/O	SD2 data 1 input and output
C22	X_SD2_DATA0	NVCC_SD2	1,8 V/ 3,3 V	I/O	SD2 data 0 input and output
C23	X_SD2_CLK	NVCC_SD2	1,8 V/ 3,3 V	O	SD2 clock output
C24	X_SD2_CMD	NVCC_SD2	1,8 V/ 3,3 V	O	SD2 command output
C25	X_SD2_DATA3	NVCC_SD2	1,8 V/ 3,3 V	I/O	SD2 data 3 input and output
C26	X_SD2_DATA2	NVCC_SD2	1,8 V/ 3,3 V	I/O	SD2 data 2 input and output
E20	X_SD2_PWR_EN	VDD_3V3	3,3 V	I	SD2 power supply enable

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Universal Asynchronous Interface
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Anchor
Universal Asynchronous Interface
Universal Asynchronous Interface

The phyCORE‑i.MX 8M Mini provides four high-speed universal asynchronous interfaces. Hardware flow control (RTS and CTS signals) may be implemented through the use of additional GPIO signals. See muxing options in NXP i.MX 8M Mini Reference Manual for more information. Location of the signals on the phyCORE-Connector:

Anchor

	UART Signals
	UART Signals

Scroll Title

anchor	UART Signal Locations
title	UART Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
C27	X_UART1_RXD	VDD_3V3_S	3,3 V	I/O	UART1 receive data
C28	X_UART1_TXD	VDD_3V3_S	3,3 V	I/O	UART1 transmit data
C29	X_UART2_RXD	VDD_3V3_S	3,3 V	I/O	UART2 receive data
C30	X_UART2_TXD	VDD_3V3_S	3,3 V	I/O	UART2 transmit data
C31	X_UART3_RXD	VDD_3V3_S	3,3 V	I/O	UART3 receive data
C32	X_UART3_TXD	VDD_3V3_S	3,3 V	I/O	UART3 transmit data
C33	X_UART4_RXD	VDD_3V3_S	3,3 V	I/O	UART4 receive data
C34	X_UART4_TXD	VDD_3V3_S	3,3 V	I/O	UART4 transmit data

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USB OTG Interfaces
Anchor
USB OTG
USB OTG

The phyCORE‑i.MX 8M Mini provides two high-speed USB OTG interfaces, which use the i.MX 8M Mini’s embedded High-Speed USB 2.0 PHY.

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Scroll Title

anchor	USB2 OTG Signal Locations
title	USB2 OTG Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A25	X_USB2_DN	VDD_3V3_S	DIFF	I/O	Negative USB2 data signal
A26	X_USB2_DP	VDD_3V3_S	DIFF	I/O	Positive USB2 data signal
A24	X_USB2_ID	VDD_3V3_S	3,3 V	I	USB2 OTG identification pin
E18	USB2_VBUS	VDD_3V3_S	Typ. 1,4 V	I	USB2 voltage bus detection

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Ethernet Interface

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...
Anchor
Ethernet
Ethernet

Connection of the phyCORE‑i.MX 8M Mini to the World Wide Web or a local area network (LAN) is possible using the onboard GbE PHY at U4. It is connected to the RGMII interface of the i.MX 8M Mini. The PHY operates with a data transmission speed of 10, 100, or 1000 Mbit/s. Alternatively, the RGMII interface which is available on the phyCORE‑Connector can be used to connect an external PHY. In this case, the onboard GbE PHY (U4) must not be populated (see L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head).

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Ethernet

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PHY (U4)

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...
Anchor
Ethernet PHY (U4)
Ethernet PHY (U4)

With an Ethernet PHY mounted at U4, the phyCORE‑i.MX 8M Mini has been designed for use in 10/100/1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE-i.MX 8M Mini Connector X1.

...

Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

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Scroll Indexterm

secondary	Ethernet Interface
tertiary	Ethernet PHY Reset
primary	Serial Interfaces

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Ethernet PHY Reset
Anchor
Ethernet PHY Reset
Ethernet PHY Reset

The Ethernet PHY at U4 can be reset via software. The reset input of the Ethernet PHY is connected to the Power-On Reset (POR) signal of the module and to the GPIO RESET_ETHPHY of the i.MX 8M Mini.

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MAC Address

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...
Anchor
MAC Address
MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Mini is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

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RGMII Interface
Anchor
RGMII Interface
RGMII Interface

In order to use an external Ethernet PHY instead of the onboard GbE PHY at U8, the RGMII interface (ENET) of the i.MX 8M Mini is brought out at phyCORE-i.MX 8M Mini Connector X1.

Note

title	Errata information

Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR011437: IOMUX: The read data is always zero when the ODE bit of ENET PHY IOs is set

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Scroll Title

anchor	RGMII Interface Signal Locations
title	RGMII Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
C1	X_ENET_RGMII_RX_CTL	VDDA_1V8	1,8 V	I	RGMII receive control signal
C2	X_ENET_RGMII_RXC	VDDA_1V8	1,8 V	I	RGMII receive clock signal
C3	X_ENET_RGMII_RD0	VDDA_1V8	1,8 V	I	RGMII receive data signal 0
C4	X_ENET_RGMII_RD1	VDDA_1V8	1,8 V	I	RGMII receive data signal 1
C5	X_ENET_RGMII_RD2	VDDA_1V8	1,8 V	I	RGMII receive data signal 2
C6	X_ENET_RGMII_RD3	VDDA_1V8	1,8 V	I	RGMII receive data signal 3
C65	X_ENET_MDIO	VDDA_1V8	1,8 V	O	RGMII Management Data Input Output
C66	X_ENET_MDC	VDDA_1V8	1,8 V	O	RGMII Management Data Clock
C67	X_ENET_RGMII_TX_CTL	VDDA_1V8	1,8 V	O	RGMII transmit control signal
C68	X_ENET_RGMII_TXC	VDDA_1V8	1,8 V	O	RGMII transmit clock signal
C69	X_ENET_RGMII_TD0	VDDA_1V8	1,8 V	O	RGMII transmit data signal 0
C70	X_ENET_RGMII_TD1	VDDA_1V8	1,8 V	O	RGMII transmit data signal 1
C71	X_ENET_RGMII_TD2	VDDA_1V8	1,8 V	O	RGMII transmit data signal 2
C72	X_ENET_RGMII_TD3	VDDA_1V8	1,8 V	O	RGMII transmit data signal 3

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SPI Interfaces
Anchor
SPI
SPI

The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI interfaces on the phyCORE‑i.MX 8M Mini Connector X1.

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Note

title	Errata information

Existing issues may be solved by refering referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR009535: ECSPI: Burst completion by SS signal in slave mode is not functional
ERR009606: ECSPI: In master mode, burst lengths of 32n+1 will transmit incorrect data
ERR009165: ECSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to be sent twice

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Scroll Title

anchor	SPI2 Interface Signal Locations
title	SPI2 Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A57	X_ECSPI2_SS0	VDD_3V3_S	3,3 V	O	SPI2 chip select signal
A58	X_ECSPI2_MOSI	VDD_3V3_S	3,3 V	O	SPI2 master out, slave in signal
A59	X_ECSPI2_MISO	VDD_3V3_S	3,3 V	I	SPI2 master in, slave out signal
A60	X_ECSPI2_SCLK	VDD_3V3_S	3,3 V	O	SPI2 serial clock output signal

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secondary	I2C Interface
primary	Serial Interfaces

I²C Interface
Anchor
I2C Interface
I2C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Mini contains four identical, independent Multimaster fast-mode I²C modules. The interface of three modules is available at the phyCORE-Connector. The first I²C module (I2C1) connects to the onboard EEPROM at U13 (I²C EEPROM), the PMIC at U3 (Power Management IC), the Real-Time Clock at U12, and the MIPI to LVDS converter at U5 L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head. The MIPI to LVDS converter connects to the I2C1 interface through the level shifter U22. The voltage domain in this part of the bus is 1,8 V.

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Scroll Title

anchor	I2C4 Interface Signal Locations
title	I2C4 Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A63	X_I2C4_SCL	VDD_3V3_S	3,3 V	OD	I2C4 serial clock output signal
A64	X_I2C4_SDA	VDD_3V3_S	3,3 V	OD-BI	I2C4 serial data input-output

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Onboard I2C Bus
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Anchor
On

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-board I2C bus
On-board I2C bus

The first I²C module (I2C1) connects to the onboard EEPROM at U13 and the PMIC at U3. The following table shows the addresses of all I2C1 devices on the phyCORE-i.MX 8M Mini:

Anchor

	I2C1 addresses
	I2C1 addresses

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anchor	I2C1 Onboard Bus Addresses
title	I2C1 Onboard Bus Addresses

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Device	Address
EEPROM (section L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head)	0x51 0x59 (factory use only)
PMIC (section L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head)	0x08
RTC	0x52
MIPI to LVDS converter	0x2D

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Synchronous Audio Interface (SAI)
Anchor
Synchronous Audio Interface (SAI)
Synchronous Audio Interface (SAI)

The phyCORE-i.MX 8M Mini features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces: SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-i.MX 8M Mini Connector X1. All signals are part of the VDD_3V3_S voltage domain.

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Note

title	Errata information

Existing issues may be solved by refering referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR050542: SAI: The Bit Count Timestamp Register (TBCTR, RBCTR) may return a live rather than latched Timestamp

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Scroll Title

anchor	SAI5 Signal Locations
title	SAI5 Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
C51	X_SAI5_RXD3	VDD_3V3_S	3,3 V	I/O	SAI5 receive data 3 signal
C52	X_SAI5_RXD2	VDD_3V3_S	3,3 V	I/O	SAI5 receive data 2signal
C53	X_SAI5_RXD1	VDD_3V3_S	3,3 V	I/O	SAI5 receive data 1 signal
C54	X_SAI5_RXD0	VDD_3V3_S	3,3 V	I/O	SAI5 receive data 0 signal
C55	X_SAI5_MCLK	VDD_3V3_S	3,3 V	I/O	SAI5 master clock signal
C56	X_SAI5_RXC	VDD_3V3_S	3,3 V	I/O	SAI5 receive bit clock signal
C57	X_SAI5_RXFS	VDD_3V3_S	3,3 V	I/O	SAI5 receive frame synchronization signal

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PCI Express Interface
Anchor
PCI Express Interface
PCI Express Interface

The 1-lane PCI Express interface of the phyCORE‑i.MX 8M Mini provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interface is fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specification. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented via the use of GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Polis) for a circuit example. The table below show the signal location for the PCIe interface.

Anchor

	PCIe Signals
	PCIe Signals

Note

title	Errata information

Existing issues may be solved by refering referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR011193: PCIE: EP, PM_PME: L1 Exit Does Not Occur when PME Service Timeout Mechanism Expires

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anchor	PCIe Interface Signal Locations
title	PCIe Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A27	X_PCIe_CLK_N	VDD_1V8	DIFF	O	PCIe negative clock signal
A28	X_PCIe_CLK_P	VDD_1V8	DIFF	O	PCIe positive clock signal
A29	X_PCIe_TXN_N	VDD_1V8	DIFF	O	PCIe negative transmit signal
A30	X_PCIe_TXN_P	VDD_1V8	DIFF	O	PCIe positive transmit signal
A31	X_PCIe_RXN_N	VDD_1V8	DIFF	I	PCIe negative receive signal
A32	X_PCIe_RXN_P	VDD_1V8	DIFF	I	PCIe positive receive signal

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General Purpose I/Os
...
Anchor
GPIOs
GPIOs

The following table lists all pins not used by any of the other interfaces described explicitly in this manual and which, therefore, can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Mini. In addition, most pins directly routed to the phyCORE-i.MX M Mini Connector X1 can be configured as GPIO due to the multiplexing functionality of the i.MX 8M Mini.

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anchor	GPIO Pin Locations
title	GPIO Pin Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
C36	X_PWM1/GPIO1_IO00	VDD_3V3_S	3,3 V	I/O	GPIO01 00 with PWM ability
C49	X_GPIO1_IO08/ETH_1588_EVENT_IN	VDD_3V3_S	3,3 V	I/O	GPIO01 08, also useable for IEEE 1588 protocol event out
C50	X_GPIO1_IO09/ETH_1588_EVENT_OUT	VDD_3V3_S	3,3 V	I/O	GPIO01 09, also useable for IEEE 1588 protocol event in
C44	X_GPIO1_IO12	VDD_3V3_S	3,3 V	I/O	GPIO01 12
A80	X_PWM2/GPIO1_IO13	VDD_3V3_S	3,3 V	I/O	GPIO01 13 with PWM ability
C46	X_PWM3/GPIO1_IO14	VDD_3V3_S	3,3 V	I/O	GPIO01 14 with PWM ability
C45	X_PWM4/GPIO1_IO15	VDD_3V3_S	3,3 V	I/O	GPIO01 15 with PWM ability

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JTAG Interface
Anchor
JTAG Interface
JTAG Interface

The phyCORE‑i.MX 8M Mini is equipped with a JTAG interface for downloading program code into the external flash, internal controller RAM, or for any debugging programs that are executed. Location of the JTAG pins on the phyCORE-i.MX 8M Mini Connector X1:

...

Warning

title	Warning

It is not possible to use both an LVDS and MIPI display at the same time. Only one type of display can be used at any given time.

...

LVDS (Flatlink)

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...
Anchor
LVDS (Flatlink)
LVDS (Flatlink)

The LVDS interface of the phyCORE-i.MX 8M Mini, using an optional MIPI to LVDS converter, is converted from the i.MX 8M Mini’s MIPI-DSI2 interface. The converter supports resolutions of up to 1920x1200 (WUXGA) at 60 frames per second with 24 bpp and reduced blanking. It is also suitable for resolutions of 1366x768 with 60 frames per second and 1280x800 at 60 frames per second, both 18 and 24 bpp. The LVDS interface is available only when U5 is mounted. Please refer to the Texas Instruments SN65DSI83 datasheet for more information.

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Scroll Title

anchor	LVDS Interface Signal Locations
title	LVDS Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A43	X_FLATLINK_D0_N/MIPI_DSI_DATA0_N	VDD_1V8	DIFF	O	Negative LVDS data 0 signal
A44	X_FLATLINK_D0_P/MIPI_DSI_DATA0_P	VDD_1V8	DIFF	O	Positive LVDS data 0 signal
A45	X_FLATLINK_D1_N/MIPI_DSI_DATA1_N	VDD_1V8	DIFF	O	Negative LVDS data 1 signal
A46	X_FLATLINK_D1_P/MIPI_DSI_DATA1_P	VDD_1V8	DIFF	O	Positive LVDS data 1 signal
A47	X_FLATLINK_D2_N/MIPI_DSI_CLK_N	VDD_1V8	DIFF	O	Negative LVDS data 2 signal
A48	X_FLATLINK_D2_P/MIPI_DSI_CLK_P	VDD_1V8	DIFF	O	Positive LVDS data 2 signal
A49	X_FLATLINK_D3_N/MIPI_DSI_DATA2_N	VDD_1V8	DIFF	O	Negative LVDS data 3 signal
A50	X_FLATLINK_D3_P/MIPI_DSI_DATA2_P	VDD_1V8	DIFF	O	Positive LVDS data 3 signal
A51	X_FLATLINK_CLK_N/MIPI_DSI_DATA3_N	VDD_1V8	DIFF	O	Negative LVDS clock signal
A52	X_FLATLINK_CLK_P/MIPI_DSI_DATA3_P	VDD_1V8	DIFF	O	Positive LVDS clock signal

...

MIPI-Display Serial Interface 2 (MIPI-DSI2)
...
Anchor
MIPI-DSI2
MIPI-DSI2

The i.MX 8M Mini’s MIPI-DSI2 interface provides resolutions of up to 1920x1080 at 60 frames per second. It uses four data channels and one clock channel. The MIPI-DSI2 interface is only available if the MIPI to LVDS converter U5 is not mounted. The interface provides a maximum bit rate of 1,5 Gbit/s.

Scroll Title

anchor	MIPI DSI-2 Interface Signal Locations
title	MIPI DSI-2 Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A43	X_FLATLINK_D0_N/MIPI_DSI_DATA0_N	VDD_1V8	DIFF	O	Negative MIPI-DSI data 0 signal
A44	X_FLATLINK_D0_P/MIPI_DSI_DATA0_P	VDD_1V8	DIFF	O	Positive MIPI-DSI data 0 signal
A45	X_FLATLINK_D1_N/MIPI_DSI_DATA1_N	VDD_1V8	DIFF	O	Negative MIPI-DSI data 1 signal
A46	X_FLATLINK_D1_P/MIPI_DSI_DATA1_P	VDD_1V8	DIFF	O	Positive MIPI-DSI data 1 signal
A47	X_FLATLINK_D2_N/MIPI_DSI_CLK_N	VDD_1V8	DIFF	O	Negative MIPI-DSI clock signal
A48	X_FLATLINK_D2_P/MIPI_DSI_CLK_P	VDD_1V8	DIFF	O	Positive MIPI-DSI clock signal
A49	X_FLATLINK_D3_N/MIPI_DSI_DATA2_N	VDD_1V8	DIFF	O	Negative MIPI-DSI data 2 signal
A50	X_FLATLINK_D3_P/MIPI_DSI_DATA2_P	VDD_1V8	DIFF	O	Positive MIPI-DSI data 2 signal
A51	X_FLATLINK_CLK_N/MIPI_DSI_DATA3_N	VDD_1V8	DIFF	O	Negative MIPI-DSI data 3 signal
A52	X_FLATLINK_CLK_P/MIPI_DSI_DATA3_P	VDD_1V8	DIFF	O	Positive MIPI-DSI data 3 signal

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MIPI CSI-2 Camera Interface
Anchor
MIPI CSI-2 Camera Interface
MIPI CSI-2 Camera Interface

The phyCORE-i.MX 8M Mini features a MIPI CSI-2 camera interface. It is routed directly to the phyCORE-i.MX 8M Mini Connector X1. The interface provides a maximum bit rate of 1,5 Gbit/s. It uses four data channels and one clock channel. All signals, including control signals and an I²C interface, to use the camera interfaces, according to PHYTEC's phyCAM‑S standard, are available at the phyCORE‑i.MX 8M Mini Connector.

...

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anchor	Camera Interface MIPI CSI-2 Signal Locations
title	Camera Interface MIPI CSI-2 Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal	SOM Voltage Domain	Signal Level	Signal Type	Description
A33	X_MIPI_CSI_DATA3_N	VDD_1V8	DIFF	I	Negative MIPI-CSI data 3 signal
A34	X_MIPI_CSI_DATA3_P	VDD_1V8	DIFF	I	Positive MIPI-CSI data 3 signal
A35	X_MIPI_CSI_DATA2_N	VDD_1V8	DIFF	I	Negative MIPI-CSI data 2 signal
A36	X_MIPI_CSI_DATA2_P	VDD_1V8	DIFF	I	Positive MIPI-CSI data 2 signal
A37	X_MIPI_CSI_CLK_N	VDD_1V8	DIFF	I	Negative MIPI-CSI clock signal
A38	X_MIPI_CSI_CLK_P	VDD_1V8	DIFF	I	Positive MIPI-CSI clock signal
A39	X_MIPI_CSI_DATA1_N	VDD_1V8	DIFF	I	Negative MIPI-CSI data 1 signal
A40	X_MIPI_CSI_DATA1_P	VDD_1V8	DIFF	I	Positive MIPI-CSI data 1 signal
A41	X_MIPI_CSI_DATA0_N	VDD_1V8	DIFF	I	Negative MIPI-CSI data 0 signal
A42	X_MIPI_CSI_DATA0_P	VDD_1V8	DIFF	I	Positive MIPI-CSI data 0 signal

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SPDIF Interface

...

...
Anchor
SPDIF Interface
SPDIF Interface

The phyCORE-i.MX 8M Mini features a SPDIF interface. It is routed directly to the phyCORE-i.MX 8M Mini Connector X1.

Note

title	Errata information

Existing issues may be solved by refering referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:

ERR050448: SPDIF: SPDIF clock limitation

...

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anchor	I2C4 Interface Signal Locations
title	I2C4 Interface Signal Locations

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SOM Connector Pin / phyBOARD-Polis Carrier Board Connector Pin	SOM Signal Name	SOM Voltage Domain	Signal Level	Signal Type	Description
A72	X_SPDIF_EXT_CLK	VDD_3V3_S	3,3 V	O	I2C4 serial clock output signal
A73	X_SPDIF_TX	VDD_3V3_S	3,3 V	O	I2C4 serial data input-output
A74	X_SPDIF_RX	VDD_3V3_S	3,3 V	I

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CPU Core Frequency Scaling
Anchor
CPU Core Frequency Scaling
CPU Core Frequency Scaling

The i.MX 8M Mini on the phyBOARD‑Polis is able to scale the clock frequency and voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as Dynamic Voltage and Frequency Scaling (DVFS).

...

These specifications describe the standard configuration of the phyCORE‑i.MX 8M Mini as of the printing of this manual.

...

.

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phyCORE-i.MX 8M Mini Power Consumption
Anchor
phyCORE-i.MX 8M MINI Power Consumption
phyCORE-i.MX 8M MINI Power Consumption

In order to illustrate the power consumption of the phyCORE-i.MX 8M Mini in various realistic load scenarios, multiple measurements were conducted. It is important to note, that these measurements are a sole depiction of the specific stresses, asserted to the SOM through the specified software applications. The given results may be utilized to dimension a power supply for the phyCORE-i.MX 8M Mini on custom hardware. Especially custom software may yield different results in power consumption compared to the values posted in the table below. It is vital that power consumption of the phyCORE-i.MX 8M Mini is evaluated when it is intended to be used with custom software.

...

Tip

title	Tip

For further information and assistance regarding your application's power consumption, please contact PHYTEC sales.

...

Low-

...

Power Modes
...
Anchor
Product Temperature Grades
Product Temperature Grades

The i.MX 8M Mini offers various low-power modes. For further, more detailed information, on how to activate and utilize the different low-power modes please refer to the PHYTEC phyCORE-i.MX 8M Mini BSP Manual and NXP i.MX 8M Mini Reference Manual. The phyCORE-i.MX 8M Mini supports the following low-power modes:

-

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Product Temperature Grades
Anchor

...

Product Temperature Grades

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Product Temperature Grades

Warning

title	Warning

The right temperature grade of the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below). If necessary, a heat spreader can be used for temperature compensation.

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title	Product Temperature Grades

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Product Temp. Grade	Controller Temp Range (Junction Temp)	RAM (Case Temp)	Others (Ambient)
I	Industrial -40°C to +105°C / Automotive -40°C to+125°C	Industrial -40°C to +95°C	Industrial -40°C to +85°C
C	Commercial 0°C to +95°C	Consumer 0°C to +95°C	Consumer 0°C to +70°C

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phyCORE-i.MX 8M Mini BGA Mounting
Anchor
BGA Mounting
BGA Mounting

The phyCORE i.MX 8M Mini uses Ball Grid Array (BGA) to mount to a carrier board (for example, phyBOARD-Polis). BGA provides several advantages:

...

Hints for Integrating and Handling the phyCORE‑i.MX 8M Mini

...

...

Integrating the phyCORE-i.MX 8M Mini
...
Anchor
Intergrating
Intergrating

Apart from this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Mini into customer applications.

The design of the phyBOARD‑Polis can be used as a reference for any customer application.
Many answers to common questions can be found at: https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/ or https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
The link “Carrier Board” within the category Dimensional Drawing leads to the layout data as shown in L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M Mini SOM as a single component of your design.
Different support packages are available for support in all stages of embedded development. Please visit http://www.phytec.de/de/support/support-pakete.html or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.
Many answers to common questions can be found at:
https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/

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Integrating the phyCORE

...

into a Target Application

...

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. As a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

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Handling the phyCORE-i

...

.MX 8M Mini
...
Anchor
Handling the phyCORE-i.MX 8M Mini
Handling the phyCORE-i

...

.MX 8M Mini

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework stations, or other desoldering methods is strongly recommended. Follow the instructions carefully for whatever method of removal is used.

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phyCORE-i.MX 8M Mini on the phyBOARD-Polis
Anchor
Polis Intro
Polis Intro

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Hardware Overview
...
Anchor
Hardware Overview
Hardware Overview

The phyBOARD‑Polis for phyCORE-i.MX 8M Mini is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M Mini microcontroller. Due to numerous standard interfaces, the phyBOARD‑Polis can serve as the bedrock for any application. At the core of the phyBOARD‑Polis is the PCL-069/phyCORE-i.MX 8M Mini System On Module (SOM) containing the processor, DRAM, eMMC, power regulation, supervision, transceivers, and other core functions required to support the i.MX 8M Mini processor. Surrounding the SOM is the PB-02820-xxxxx.Ax/phyBOARD‑Polis carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCL-069 System On Module connects to the phyBOARD‑Polis carrier board using a Ball Grid Array (BGA). The PCL-069 SOM is soldered directly onto the phyBOARD‑Polis using PHYTEC's Direct Solder Connect technology. This solution offers an ultra-low-cost Single Board Computer for the i.MX 8M Mini processor, while maintaining most of the advantages of the SOM concept.

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phyBOARD-

...

Polis Concept
...
Anchor
phyBOARD-Polis Concept

...

phyBOARD-Polis Concept

phyCORE carrier boards are designed and tested to be used in:

series products
evaluating, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer-designed applications.

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy.

...

The phyCORE-i.MX 8M Mini module populated with the i.MX 8M Mini microprocessor and all applicable SOM circuitry such as LPDDR 4 SDRAM, managed NAND, Ethernet transceiver, WiFi, and PMIC to name a few.
The phyBOARD-Polis carrier board offers all essential components and connectors for a start-up including a power supply for 24 V input voltage, and interface connectors such as USB micro-AB, USB A, and Ethernet RJ-45 which enable the use of the SOM’s interfaces with standard cables.

The carrier board can also serve as a reference design for the development of custom target hardware in which the phyCORE SOM is deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

...

SBCplus Concept ...
Anchor
SBCplus Concept
SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time to market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") that are continuously being refined and updated.

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Tip

title	Tip

For further information, please contact PHYTEC sales.

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phyBOARD-Polis Features

...

...
Anchor
phyBOARD-Polis Features
phyBOARD-Polis Features

The phyBOARD‑Polis i.MX 8M Mini supports the following features:

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Warning

title	Warning

Cite summary

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phyBOARD-Polis Block Diagram

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...
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anchor phyBOARD-Polis Block Diagram
title phyBOARD-Polis Block Diagram
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phyBOARD-

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Polis Component Placement

Scroll Title

anchor	phyBOARD-Polis Components (Top)
title	phyBOARD-Polis Components (Top)

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Scroll Title

anchor	phyBOARD-Polis Components (Bottom)
title	phyBOARD-Polis Components (Bottom)

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phyBOARD-Polis Component Overview
Anchor
phyBOARD-Polis Components
phyBOARD-Polis Components

The phyBOARD‑Polis features many different interfaces and is equipped with the components listed in table L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head. For a more detailed description of each component, refer to the appropriate section listed in the table below. L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head and L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head highlight the location of each component for easy identification.

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secondary	phyBOARD-Polis Component Overview
tertiary	Connectors and Pin Headers
primary	phyCORE-i.MX 8M Mini on the phyBOARD-Polis

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Connectors and Pin Headers
Anchor
Connectors and Pin Headers
Connectors and Pin Headers

This is a list of all available connectors on the phyBOARD-Polis.

...

Warning

title	Warning

Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user 's responsibility to must take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

...

LEDs

The phyBOARD-Polis is populated with one LED, which is user-programmable. L-862e.Ax phyCORE-i.MX 8M Mini/phyBOARD-Polis (1518.1a / 1532.1) HW Manual Head shows the location of the LED.

Scroll Title

anchor	phyBOARD-Polis LED Description
title	phyBOARD-Polis LED Description

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LED	Color	Description	Section
D11	RGB	User-programmable RGB LED	Multicolor LED

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Switches

...

...
Anchor
phyBOARD-Polis Switches
phyBOARD-Polis Switches

The phyBOARD-Polis is populated with 3 switches. The tables below show their function:

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Boot Selection (see Multi-port Switch)
SD-Card or WIFI Selection
UART3 destination (A/V or FTDI) (see USB Debug)

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Jumpers
...
Anchor
Jumpers
Jumpers

The phyBOARD-Polis comes pre-configured with several solder jumpers (J). The jumpers enable the flexible configuration of a limited number of features for development purposes.

Warning

title	Warning

Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Contact our sales team if you need jumper configurations different from the default configuration.

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.

...

phyBOARD-Polis SBC Component Details
Anchor
phyBOARD-Polis SBC Component Details
phyBOARD-Polis SBC Component Details

This section provides a more detailed look at the phyBOARD‑Polis components. Each subsection details a particular connector/interface for configuring that interface.

Tip

title	Tip

Where possible, we also provide any useful information regarding design consideration considerations for components. This can be used if you plan to design your own carrier board.

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.

...

phyCORE-Connection (X3)

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anchor	phyCORE Connector (X3)
title	phyCORE Connector (X3)

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Power

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Supply (X33)

...

...
Anchor
Power Supply (X33)
Power Supply (X33)

Warning

title	Warning

Do not change modules or jumper settings while the phyBOARD‑Polis is supplied with power!

...

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anchor	X33 Pin Assignment
title	X33 Pin Assignment

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Interface Pin #	Signal	Description
1	VCC_IN_24V	24 V power supply
2	GND	Ground

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Power Design Considerations

It is recommended to route high current rails, like the SOM supply voltage, as planes to keep series resistance at a minimum. The same thing should be applied to ground paths. For more information, see phyCORE-i.MX 8M Mini Power Consumption.

...

. For more information, see phyCORE-i.MX 8M Mini

...

Power Consumption.

UART Connectivity (X8 and X9)

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anchor	UART Connector (X9)
title	UART Connector (X9)

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anchor	X9 Pin Assignment
title	X9 Pin Assignment

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Interface Pin #	Signal	Pin #	Signal
1	NC	2	NC
3	UART1_RXD_RS232	4	UART1_RTS_RS232
5	UART1_TXD_RS232	6	UART1_CTS_RS232
7	UART1_RS485_A	8	UART1_RS485_B
9	GND	10	NC

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UART Design Consideration

...

When designing a custom carrier board, remember the TTL level is 3.3 V. Route signals as single-ended 50 Ohm lines.

...

Ethernet Connectivity (X1)

...

Scroll Title

anchor	Ethernet Connector (X1)
title	Ethernet Connector (X1)

The phyBOARD‑Polis is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK LINK (green) and ACTIVITY (yellow) indication indications are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

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title	X1 Pin Assignment

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Interface Pin #	Signal name	Signal Type	Signal Level	Description
1	X_ETH_A_P	Ethernet	Analog	D1+
2	X_ETH_A_N	Ethernet	Analog	D1-
3	X_ETH_B_P	Ethernet	Analog	D2+
4	X_ETH_B_N	Ethernet	Analog	D2-
5	GND	-	-	MDCT1
6	GND	-	-	MDCT2
7	X_ETH_C_P	Ethernet	Analog	D3+
8	X_ETH_C_N	Ethernet	Analog	D3-
9	X_ETH_D_P	Ethernet	Analog	D4+
10	X_ETH_D_N	Ethernet	Analog	D4-
11	VCC_3V3	Ethernet	3.3 V	LED_GR_A
12	X_ETH0_LED0_LINK	Ethernet	Analog	LED_GR_C
13	VCC_3V3	Ethernet	3.3 V	LED_YE_A
14	X_ETH0_LED2_ACT	Ethernet	Analog	LED_YE_C

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Ethernet

...

Design Consideration

...

...
The data lanes should be routed with a differential impedance of 100 Ohm and kept as short as possible. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a suitable resistor.
...
LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a suitable resistor.

USB OTG and 2.0 Connectivity (X2 and X5)

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anchor	USB OTG and 2.0 Connectors (X2 and X5)
title	USB OTG and 2.0 Connectors (X2 and X5)

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Scroll Title

anchor	USB 2.0 - X5 Pin Assignment
title	USB 2.0 - X5 Pin Assignment

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Interface Pin #	Signal name	Signal Level	Signal Type	Description
1	USB_HUB_VBUS1	5 V	PWR_I	5 V USB supply voltage
2	USB_HUB_DM1	Diff	USB_I/O	Negative USB HUB1 data signal
3	USB_HUB_DP1	Diff	USB_I/O	Positive USB HUB1 data signal
4	GND	-	-	Ground
S1	SHIELD1	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
S2	SHIELD2	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
S3	SHIELD3	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
S4	SHIELD4	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm

...

USB Design Consideration

...

The data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.

...

USB Debug (X30)

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anchor	USB Debug Connector (X30)
title	USB Debug Connector (X30)

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title	X30 Pin Assignment

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Interface Pin #	Signal name	Signal Level	Signal Type	Description
1	VBUS_DEBUG_USB	5 V	PWR_I	5 V USB supply voltage
2	DEBUG_USB_DM	Diff	USB_I/O	Negative debug USB data signal
3	DEBUG_USB_DP	Diff	USB_I/O	Positive debug USB data signal
4	DEBUG_USB_ID	3,3 V	I	Debug USB identification signal (not connected)
5	GND	-	-	Ground
6	SHIELD1	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
7	SHIELD2	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
8	SHIELD3	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
9	SHIELD4	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
10	SHIELD5	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm
11	SHIELD6	Shield	-	Shield connected to Ground over 2,2 nF parallel to 1 MOhm

...

Debug Design Considerations

...

The UART data signals to the UART to USB converter should be routed as singled-ended signals with an impedance of 50 Ohm and kept as short as possible. The USB data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.

...

possible.

Secure Digital Memory / MultiMedia Card (X4)

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anchor	SD-Card / MM Card Connector (X4)
title	SD-Card / MM Card Connector (X4)

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title	X4 Pin Assignment

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Interface Pin #	Signal name	Signal Level	Signal Type	Description
1	X_SD2_DATA2	1,8 V/3,3 V	I/O	SD2 data 2
2	X_SD2_DATA3	1,8 V/3,3 V	I/O	SD2 data 3
3	X_SD2_CMD	1,8 V/3,3 V	O	SD2 command
4	VCC_3V3	3,3 V	PWR_I	3,3 V supply voltage
5	X_SD2_CLK	1,8 V/3,3 V	O	SD2 clock
6	GND			Ground
7	X_SD2_DATA0	1,8 V/3,3 V	I/O	SD2 data 0
8	X_SD2_DATA1	1,8 V/3,3 V	I/O	SD2 data 1
9	X_SD2_CD_B	1,8 V/3,3 V	I	SD2 card detect
10	GND	-	-	Ground
11	GND	-	-	Ground
12	GND	-	-	Ground
13	GND	-	-	Ground
14	GND	-	-	Ground

...

SD / MM Card Design Considerations

Series resistors in data and clock signals should be placed as close as possible to the signal source. For I/O signals this means two resistors in one electric net are recommended. The voltage of the SD2 signal lanes is NVCC_SD2 and can switch between 1.8 V and 3.3 V. The supply voltage of the SD-Card remains 3.3 V and should not be connected to NCVV_SD2. All signals should be routed as 50 Ohm singledsingle-ended lines.

...

PCIe Connectivity (X6)

...

...
Scroll Title
anchor PCIe Connector (X6)
title PCIe Connector (X6)
...
Scroll Title
anchor X6 Pin Assignment
title X6 Pin Assignment
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cellHighlighting true
Interface Pin #
Signal name
Signal Level
Signal Type
Description
1
X_SAI1_RXD5/BOOT_CFG[5]
3,3 V
O
X_SAI1_RXD5/BOOT_CFG[5] switches nWAKE
High level only possible when nPOR_IN_DELAYED is not active (low)
2
VCC_3V3
3,3 V
PWR_I
Supply voltage 3,3 V
3
X_SAI1_TXD0/BOOT_CFG[8]
3,3 V
IO
PCI express reserved
4
GND
-
-
Ground
5
X_SAI5_TXD7
3,3 V
IO
PCI express reserved
6
VCC_1V5
1,5 V
PWR_I
Supply voltage 1,5 V
7
X_PCIE2_CLKREQ_B
-
-
PCI express clock request
8
NC
-
-
Not connected
9
GND
-
-
Ground
10
NC
-
-
Not connected
11
X_PCIe_CLK_N
Diff
PCIe_O
Negative PCIe clock signal
12
NC
-
-
Not connected
13
X_PCIe_CLK_P
Diff
PCIe_O
Positive PCIe clock signal
14
NC
-
-
Not connected
15
GND
-
-
Ground
16
NC
-
-
Not connected
17
NC
-
-
Not connected
18
GND
-
-
Ground
19
NC
-
-
Not connected
20
NC
-
-
Not connected
21
GND
-
-
Ground
22
miniPCIe_nPERST
3,3 V
O
PCI express reset
23
X_PCIE_RXN_N
Diff
PCIe_I
Negative PCIe receive signal
24
VCC_3V3
3,3 V
PWR_I
Supply voltage 3,3 V
25
X_PCIE_RXN_P
Diff
PCIe_I
Positive PCIe receive signal
26
GND
-
-
Ground
27
GND
-
-
Ground
28
VCC_1V5
1,5 V
PWR_I
Supply voltage 1,5 V
29
GND
-
-
Ground
30
X_I2C2_SCL
3,3 V
OD
I2C2 serial clock
31
X_PCIE_TXN_N
Diff
PCIe_O
Negative PCIe transmit signal
32
X_I2C2_SDA
3,3 V
OD-BI
I2C2 serial data signal
33
X_PCIE_TXN_P
Diff
PCIe_O
Positive PCIe transmit signal
34
GND
-
-
Ground
35
GND
-
-
Ground
36
USB_HUB_DM3
Diff
USB_I/O
Negative USB HUB 3 signal
37
GND
-
-
Ground
38
USB_HUB_DP3
Diff
USB_I/O
Positive USB HUB 3 signal
39
VCC_3V3
3,3 V
PWR_I
Supply voltage 3,3 V
40
GND
-
-
Ground
41
VCC_3V3
3,3 V
PWR_I
Supply voltage 3,3 V
42
TP1
-
-
Test pad 1
43
GND
-
-
Ground
44
TP2
-
-
Test pad 2
45
NC
-
-
Not connected
46
TP3
-
-
Test pad 3
47
NC
-
-
Not connected
48
VCC_1V5
1,5 V
PWR_I
Supply voltage 1,5 V
49
NC
-
-
Not connected
50
GND
-
-
Ground
51
NC
-
-
Not connected
52
VCC_3V3
3,3 V
PWR_I
Supply voltage 3,3 V
S1
GND
-
-
Ground
S2
GND
-
-
Ground
...

PCIe

...

Design Considerations

...

100nF AC-Coupling capacitors are placed close to output pins of the i.MX 8M Mini on the PCL-069 in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm.

Camera Connections

...

100nF AC-Coupling capacitors are placed close to output pins of the
...
i.MX 8M Mini on the
...
PCL-069 in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm.

Camera Connections

phyCAM-M MIPI CSI-2 Camera Connector (X10)

Scroll Title

anchor	phyCAM-M MIPI CSI-2 Camera Connector (X10)
title	phyCAM-M MIPI CSI-2 Camera Connector (X10)

phyCAM-M MIPI CSI-2 Camera Connector (X10)

...

Scroll Title

anchor	X10 Pin Assignment
title	X10 Pin Assignment

Scroll Table Layout

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cellHighlighting	true

Interface Pin #	Signal Name	Signal Level	Signal Type	Description
1	GND	-	-	Ground
2	X_MIPI_CSI_DATA0_P	Diff	CSI2_I	Positive MIPI CSI data 0 signal
3	X_MIPI_CSI_DATA0_N	Diff	CSI2_I	Negative MIPI CSI data 0 signal
4	GND	-	-	Ground
5	X_MIPI_CSI_DATA1_P	Diff	CSI2_I	Positive MIPI CSI data 1 signal
6	X_MIPI_CSI_DATA1_N	Diff	CSI2_I	Negative MIPI CSI data 1 signal
7	GND	-	-	Ground
8	X_MIPI_CSI_CLK_P	Diff	CSI2_I	Positive MIPI CSI clock signal
9	X_MIPI_CSI_CLK_N	Diff	CSI2_I	Negative MIPI CSI clock signal
10	GND	-	-	Ground
11	X_MIPI_CSI_DATA2_P	Diff	CSI2_I	Positive MIPI CSI data 2 signal
12	X_MIPI_CSI_DATA2_N	Diff	CSI2_I	Negative MIPI CSI data 2 signal
13	GND	-	-	Ground
14	X_MIPI_CSI_DATA3_P	Diff	CSI2_I	Positive MIPI CSI data 3 signal
15	X_MIPI_CSI_DATA3_N	Diff	CSI2_I	Negative MIPI CSI data 3 signal
16	GND	-	-	Ground
17	X_SAI2_TXD0	3,3 V	IO	Multipurpose pin 4
18	X_SAI1_TXFS	3,3 V	IO	Multipurpose pin 3
19	X_SAI1_MCLK	3,3 V	IO	Multipurpose Pin 2 / Default = TRIGGER (IN)
20	X_SD2_RESET_B	1,8 V/ 3,3 V	OD	CSI reset signal
21	GND	-	-	Ground
22	X_I2C4_SCL	3,3 V	OD	I2C4 serial clock signal
23	X_I2C4_SDA	3,3 V	OD_BI	I2C4 serial data signal
24	CSI1_I2C_ADR	3,3 V	OD	I2C4 address select
25	CSI1_ nRESET	3,3 V		Camera reset signal
26	CSI1_VCC_SELECT	3,3 V		Set voltage on VCC pins
27	GND	-	-	Ground
28	VCC_CAM_CSI1	3,3 V/ 5 V	PWR_I	CSI supply voltage 3,3 V or 5 V
29	VCC_CAM_CSI1	3,3 V/ 5 V	PWR_I	CSI supply voltage 3,3 V or 5 V
30	VCC_CAM_CSI1	3,3 V/ 5 V	PWR_I	CSI supply voltage 3,3 V or 5 V

...

CAN FD (X7)

...

...
Scroll Title
anchor CAN FD (X7)
title CAN FD (X7)
...
Scroll Title
anchor X7 Pin Assignment
title X7 Pin Assignment
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Interface Pin #
Signal Name
Signal Level
Signal Type
Description
1 NC - - -
2 GND - - Ground
3 X_CAN_L Diff CAN_I/O CAN FD low signal
4 X_CAN_H Diff CAN_I/O CAN FD high signal
5 GND - - Ground
6 NC - - -
7 NC - - -
8 NC - - -
9 NC - - -
10 NC- - -
...
-
...
...

Audio/Video Connectors (X16 and X18)

...

Scroll Title

anchor	Audio/Video Connectors (X16 and X18)
title	Audio/Video Connectors (X16 and X18)

...

Cite summary

showCitationLinks	false
local	true

...

A/V Design Consideration
All signals should be routed as short as possible and as 50 Ohm single-ended lines.
...
as possible and as 50 Ohm single-ended lines.
Voice Array Connector (X38)
Scroll Title
anchor Voice Array Connector (X38)
title Voice Array Connector (X38)
...
Scroll Title
anchor X38 Pin Assignment
title X38 Pin Assignment
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Interface Pin #
Signal Name
Signal Level
Signal Type
Description
1
VCC_5V
5 V PWR_I 5 V supply voltage
2
VCC_3V3
3,3 V PWR_I 3,3 V supply voltage
3
X_UART4_TXD
3,3 V
O
UART4 transmit data
4
X_UART4_RXD
3,3 V
I
UART4 receive data
5
X_I2C3_SCL
3,3 V
O
I2C3 serial clock
6
X_I2C3_SDA
3,3 V
IO
I2C3 serial data
7
X_SAI1_MCLK
3,3 V
IO
SAI1 master clock
8
X_SAI1_RXC
3,3 V
IO
SAI1 receive bit clock
9
X_SAI1_RXD0/BOOT_CFG[0]
3,3 V
IO
SAI1 receive data 0
10
X_SAI1_RXD1/BOOT_CFG[1]
3,3 V
IO
SAI1 receive data 1
11
X_SAI1_RXD2/BOOT_CFG[2]
3,3 V
IO
SAI1 receive data 2
12
X_SAI1_RXD3/BOOT_CFG[3]
3,3 V
IO
SAI1 receive data 3
13
GND
-
-
Ground
14
GND
-
-
Ground
15
X_SAI2_MCLK
3,3 V
IO
SAI2 master clock
16
X_SAI2_TXC
3,3 V
IO
SAI2 transmit bit clock
17
X_SAI2_TXD0
3,3 V
IO
SAI2 transmit data 0
18
X_SAI1_RXD4/BOOT_CFG[4]
3,3 V
IO
SAI1 receive data 4
...
...

Voice Array
...
Design Considerations
All signals should be routed as short as possible and as 50 Ohm single-ended lines.
...
...
Expansion Connector (X8)
...
...
Scroll Title
anchor Expansion Connector (X8)
title Expansion Connector (X8)
...
Scroll Title
anchor X8 Expansion Connector Pin Assignment
title X8 Expansion Connector Pin Assignment
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Interface Pin #
Signal Name
Signal Level
Signal Type
Description
1
VCC_3V3
3,3 V
PWR_I
3,3 V supply voltage
2
VCC_5V
5 V
PWR_I
5 V supply voltage
3
VCC_1V5
1,5 V
PWR_I
1,5 V supply voltage
4
GND
-
-
Ground
5
X_ECSPI1_SS1
3,3 V
OD
SPI1 chip select
6
X_ECSPI1_MOSI
3,3 V
O
SPI1 master out slave in
7
X_ECSPI1_MISO
3,3 V
I
SPI1 master in slave out
8
X_ECSPI1_SCLK
3,3 V
O
SPI1 serial clock
9
GND
-
-
Ground
10
X_UART3_RXD_EXP
3,3 V
I
UART3 receive data
11
X_I2C3_SDA
3,3 V
OD_BI
I2C3 serial data
12
X_UART3_TXD_EXP
3,3 V
O
UART3 transmit data
13
X_I2C3_SCL
3,3 V
OD
I2C3 serial clock
14
GND
-
-
Ground
15
X_JTAG_TMS
3,3 V
I
JTAG test mode select
16
X_JTAG_TRST_B
3,3 V
I
JTAG tap reset
17
X_JTAG_TDI
3,3 V
I
JTAG data in
18
X_JTAG_TDO
3,3 V
O
JTAG data out
19
GND
-
-
Ground
20
X_JTAG_TCK
3,3 V
I
JTAG clock
21
USB_HUB_DP4
Diff
USB_I/O
Positive USB HUB 4 signal
22
USB_HUB_DM4
Diff
USB_I/O
Negative USB HUB 4 signal
23
X_nRESET_IN
3,3 V
OD
Open drain SoM reset input
24
GND
-
-
Ground
25
X_SPDIF_TX
3,3 V
O
SPDIF transmit data
26
X_SPDIF_RX
3,3 V
I
SPDIF receive data
27
X_SPDIF_EXT_CLK
3,3 V
O
SPDIF clock
28
X_nPOR_OD
3,3 V
OD
Open drain SoM Power-On Reset output
29
GND
-
-
Ground
30
X_TEST_MODE
3,3 V
I
Test Mode signal (boot signal for i.MX 8M Nano)
31
UART4_RXD
3,3 V
I
UART4 receive data
32
X_SAI1_TXD1 / BOOT_MODE_CFG[9]
3,3 V
I/O
SAI1 transmit data 1
33
UART4_TXD
3,3 V
O
UART4 transmit data
34
GND
-
-
Ground
35
X_SAI1_TXD2 / BOOT_MODE_CFG[10]
3,3 V
I/O
SAI1 transmit data 2
36
X_SAI1_TXD3 / BOOT_MODE_CFG[11]
3,3 V
I/O
SAI1 transmit data 3
37
X_SAI1_TXD4 / BOOT_MODE_CFG[12]
3,3 V
I/O
SAI1 transmit data 4
38
X_SAI1_TXD5 / BOOT_MODE_CFG[13]
3,3 V
I/O
SAI1 transmit data 5
39
X_SAI1_TXD6 / BOOT_MODE_CFG[14]
3,3 V
I/O
SAI1 transmit data 6
40
X_CLKIN1
1,8 V
I
Serial clock 1 input
41
GND
-
-
Ground
42
X_CLKOUT1
1,8 V
O
Serial clock 1 output
43
X_POR_IN
3,3 V
I
SoM Power-On Reset input
44
X_ETH_JTAG_TDI
1,8 V
I
Ethernet JTAG data in
45
X_ ETH_JTAG_TMS
1,8 V
I
Ethernet JTAG test mode
46
GND
-
-
Ground
47
X_ ETH_JTAG_TDO
1,8 V
O
Ethernet JTAG data out
48
X_ ETH_JTAG_CLK
1,8 V
I
Ethernet JTAG clock
49
X_ ETH_GPIO1
1,8 V
I/O
Ethernet GPIO1
50
X_CLKIN2
1,8 V
I
Serial clock 2 input
51
GND
-
-
Ground
52
X_CLKOUT2
1,8 V
O
Serial clock 2 output
53
USB_HUB_PRTPWR4
5 V
I
USB HUB 4 power enable
54
USB_HUB_nOSC4
5 V
I
USB HUB 4 over current sense
55
X_RTC_INT
3,3 V
O
RTC interrupt output
56
GND
-
-
Ground
57
VCC_IN_24V
24 V
PWR_I
24 V board input voltage
58
nPOR_IN_DELAYED
3,3 V
O
SoM Power-On Reset delayed
59
GND
-
-
Ground
60
VCC_5V_REG
5 V
PWR_I
5 V supply voltage
...
...

...
Expansion Connector Design Consideration
...
All signals should be routed as short as possible and as 50 Ohm single-ended lines.
...
.
...
I²C Connectivity
The I²C interfaces of the i.MX 8M Mini are available at different connectors on the phyBOARD‑Polis. The following table provides a list of the connectors and pins with I²C connectivity:
Scroll Title
anchor I2C Connectivity Interface Connections
title I2C Connectivity Interface Connections
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Interface
Interface Pin #
Signal Name Signal Level Signal Type
X18
24
I2C3_SCL 3,3 V
O
X18 22 I2C3_SDA 3,3 V I/O
X8
13
I2C3_SCL 3,3 V O
X8 11 I2C3_SDA 3,3 V I/O
X38
5
I2C3_SCL 3,3 V O
X38 6 I2C3_SDA 3,3 V I/O
X10 23 I2C4_SCL 3,3 V O
X10 24 I2C4_SDA 3,3 V I/O
Onboard Functionalities
...
I/O

Onboard Functionalities
...
Trusted Platform Module (TPM)
The phyBOARD-Polis is equipped with a Trusted Platform Module (TPM). The TPM is a chip developed, produced, tested, and certified according to the TCG specification that enhances the board with additional security functions. These security functions include the generation and secure storage (in the hardware) of keys for the authentication and identification of communication participants (SSH, server, cloud, etc.) and data, which can also be encrypted.
...
Tip
title Tip
For more information about your security needs, contact a PHYTEC salesperson.
...
...
Wireless WLAN and Bluetooth Transceiver Module
...
...
Anchor
Antenna Module
Antenna Module
The phyBOARD-Polis is equipped with a Wireless WLAN and Bluetooth Transceiver Module that is capable of providing WLAN and Bluetooth functionality. The module requires a UART with handshake capability and a 4-bit SDIO interface. The module is connected to the SOM through the following interfaces:
Scroll Title
anchor Wireless WLAN and Bluetooth Transceiver Module Interface Connections
title Wireless WLAN and Bluetooth Transceiver Module Interface Connections
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Interface Pin #
Signal Name
Signal Level
Signal Type
Description
22
X_SD1_DATA0
3,3 V
I/O SD1 data 0
23
X_SD1_DATA1
3,3 V
I/O SD1 data 1
25
X_SD1_DATA2
3,3 V
I/O SD1 data 2
26
X_SD1_CMD
3,3 V
O SD1 command
27
X_SD1_DATA3
3,3 V
I/O SD1 data 3
29
X_SD1_CLK
3,3 V
O SD1 clock
31 X_SAI3_RXD/UART2_RTS_B
3,3 V
I/O UART2 request to send
32 X_SAI3_RXC/UART2_CTS_B
3,3 V
I/O UART2 clear to send
33 X_SAI3_TXC/UART2_TX
3,3 V
I/O UART2 transmit data
34 X_SAI3_TXFS/UART2_RX
3,3 V
I/O UART2 receive data
21 X_SD1_DATA4
3,3 V
I/O SD1 data 4
12 X_SD1_DATA5
3,3 V
I/O SD1 data 5
39 X_SD1_DATA6
3,3 V
I/O SD1 data 6
40 X_SD1_DATA7
3,3 V
I/O SD1 data 7
...
...

LEDs and Switches
...
Scroll Title
anchor phyBOARD-Polis Switches and LED Locations
title phyBOARD-Polis Switches and LED Locations
...
...
Multicolor (RGB) LED (D11)
...
...
The phyBOARD-Polis provides one multicolor (RGB) LED (D11). The table below shows the signals that control colors:
...
All signals should be routed as short as possible and as 50 Ohm single-ended lines.
...
.
...
Switches
Multi-port Switch (S1)
The phyBOARD‑Polis features a multi-port switch with six individually switchable ports. This switch controls the SOM boot mode, SOM boot configuration, UART functionality, and USB configuration when i.MX 8M NANO is mounted on the carrier board. The figures below show a visual representation of each S1 switch setting:
...
The phyBOARD-Polis is equipped with an ON/OFF button at S3. For more information on the ON/OFF switch, refer to the i.XM 8M Mini Reference Manual.
...
Revision History
Scroll Title
anchor Revision History
title Revision History
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Date
Version Numbers
Changes in this Manual
25.10.2019
Manual
L-862e.A0

Preliminary Edition.
Describes the phyCORE‑i.MX 8M Mini
SOM Version: 1518.1a
Describes the phyBOARD-Polis
PCB Version: 1532.0
03.07.2020 L-862e.A1
PCB Revision: 1532.1
Updated PCB Figures and content
Section: Power Consumption Updated
21.04.2021 L-862e.A2 Added section: Unused Signals
Updated section: System Boot Configuration
Updated section: i.MX 8M Mini System Boot Settings
Added section: i.MX 8M Nano System Boot Settings
xx.08.2022 L-862e.A3

...

Page tree

Page History

Versions Compared

Old Version 354

New Version 355

Key

Design Considerations

Ordering Information

Product Specific Information and Technical Support

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Mini

Image Modified

Product Change Management and Information Regarding Parts Populated on the SOM / SBC... AnchorPCMPCM

PHYTEC Documentation

Conventions

Types of Signals

Abbreviations and Acronyms AnchorAbbreviations and Acronyms Abbreviations and Acronyms

phyCORE‑i.MX 8M Mini Features

phyCORE-i.MX 8M Mini Block Diagram... AnchorphyCORE-i.MX8M Mini Block DiagramphyCORE-i.MX8M Mini Block Diagram

phyCORE-i.MX 8M Mini Component Placement AnchorphyCORE-i.MX 8M Mini Component PlacementphyCORE-i.MX 8M Mini Component Placement

phyCORE-i.MX 8M Mini Minimal Operating Requirements... AnchorphyCORE-i.MX 8M Mini Minimal Operating RequirementsphyCORE-i.MX 8M Mini Minimal Operating Requirements

Pin Description... AnchorPin DescriptionPin Description

Unused Signals AnchorPin DescriptionPin Description

Primary System Power (VDD_3V3) AnchorPrimary System Power (VDD_3V3)Primary System Power (VDD_3V3)

Power Management IC (PMIC)(U3)

... AnchorPower Management IC (PMIC)(U3)Power Management IC (PMIC)(U3)

Power Domains

... AnchorPower DomainsPower Domains AnchorphyCORE-i.MX 8M Mini Powering SchemephyCORE-i.MX 8M Mini Powering Scheme

External Logic Supply Voltage

... AnchorExternal Logig Supply VoltageExternal Logig Supply Voltage

Backup Power (VBAT)... AnchorBackup PowerBackup Power

On-Board RTC and RTC Backup Power (VRTC)... AnchorBackup Power

Backup Power

Reset AnchorResetReset

System Boot Configuration AnchorSystem Boot ConfigurationSystem Boot Configuration

System Boot

Configuration

i.MX 8M Mini System Boot Settings

Boot Mode Selection... AnchorBoot Mode SelectionBoot Mode Selection

Boot

Device Selection and

Configuration... AnchorBoot Device Selection and ConfigurationBoot Device Selection and Configuration

i.MX 8M Nano System Boot Settings AnchorSystem Boot ConfigurationSystem Boot Configuration

LPDDR4-RAM (U2)... AnchorLPDDR4-RAM (U2)LPDDR4-RAM (U2)

QUAD SPI-NOR (U7) AnchorQUAD SPI-NOR (U7)QUAD SPI-NOR (U7)

eMMC Flash Memory (U21)

... AnchoreMMC Flash Memory (U21)eMMC Flash Memory (U21)

I2C EEPROM (U13) AnchorI2C EEPROM (U13)I2C EEPROM (U13)

EEPROM Write Control

... AnchorEEPROM Write ControlEEPROM Write Control

SDIO Interfaces... AnchorSDIO InterfacesSDIO Interfaces

Universal Asynchronous Interface... AnchorUniversal Asynchronous InterfaceUniversal Asynchronous Interface

USB OTG Interfaces AnchorUSB OTGUSB OTG

Ethernet Interface

... AnchorEthernetEthernet

Ethernet

PHY (U4)

... AnchorEthernet PHY (U4)Ethernet PHY (U4)

Ethernet PHY Reset AnchorEthernet PHY ResetEthernet PHY Reset

MAC Address

... AnchorMAC AddressMAC Address

RGMII Interface AnchorRGMII InterfaceRGMII Interface

SPI Interfaces AnchorSPISPI

I2C Interface AnchorI2C InterfaceI2C Interface

Onboard I2C Bus... AnchorOn

-board I2C busOn-board I2C bus

Synchronous Audio Interface (SAI) AnchorSynchronous Audio Interface (SAI)Synchronous Audio Interface (SAI)

PCI Express Interface AnchorPCI Express InterfacePCI Express Interface

General Purpose I/Os... AnchorGPIOsGPIOs

JTAG Interface AnchorJTAG InterfaceJTAG Interface

LVDS (Flatlink)

... AnchorLVDS (Flatlink)LVDS (Flatlink)

MIPI-Display Serial Interface 2 (MIPI-DSI2)... AnchorMIPI-DSI2MIPI-DSI2

MIPI CSI-2 Camera Interface AnchorMIPI CSI-2 Camera InterfaceMIPI CSI-2 Camera Interface

SPDIF Interface

... AnchorSPDIF InterfaceSPDIF Interface

CPU Core Frequency Scaling AnchorCPU Core Frequency ScalingCPU Core Frequency Scaling

phyCORE-i.MX 8M Mini Power Consumption AnchorphyCORE-i.MX 8M MINI Power ConsumptionphyCORE-i.MX 8M MINI Power Consumption

Low-

Power Modes... AnchorProduct Temperature GradesProduct Temperature Grades

Product Temperature Grades Anchor

Product Change Management and Information Regarding Parts Populated on the SOM / SBC
...
Anchor
PCM
PCM

Abbreviations and Acronyms
Anchor
Abbreviations and Acronyms
Abbreviations and Acronyms

phyCORE-i.MX 8M Mini Block Diagram
...
Anchor
phyCORE-i.MX8M Mini Block Diagram
phyCORE-i.MX8M Mini Block Diagram

phyCORE-i.MX 8M Mini Component Placement
Anchor
phyCORE-i.MX 8M Mini Component Placement
phyCORE-i.MX 8M Mini Component Placement

phyCORE-i.MX 8M Mini Minimal Operating Requirements
...
Anchor
phyCORE-i.MX 8M Mini Minimal Operating Requirements
phyCORE-i.MX 8M Mini Minimal Operating Requirements

Pin Description
...
Anchor
Pin Description
Pin Description

Unused Signals
Anchor
Pin Description
Pin Description

Primary System Power (VDD_3V3)
Anchor
Primary System Power (VDD_3V3)
Primary System Power (VDD_3V3)

...
Anchor
Power Management IC (PMIC)(U3)
Power Management IC (PMIC)(U3)

...
Anchor
Power Domains
Power Domains
Anchor
phyCORE-i.MX 8M Mini Powering Scheme
phyCORE-i.MX 8M Mini Powering Scheme

...
Anchor
External Logig Supply Voltage
External Logig Supply Voltage

Backup Power (VBAT)
...
Anchor
Backup Power
Backup Power

On-Board RTC and RTC Backup Power (VRTC)
...
Anchor
Backup Power

Reset
Anchor
Reset
Reset

System Boot Configuration
Anchor
System Boot Configuration System Boot Configuration

Boot Mode Selection
...
Anchor
Boot Mode Selection
Boot Mode Selection

Configuration
...
Anchor
Boot Device Selection and Configuration
Boot Device Selection and Configuration

i.MX 8M Nano System Boot Settings
Anchor
System Boot Configuration
System Boot Configuration

LPDDR4-RAM (U2)
...
Anchor
LPDDR4-RAM (U2)
LPDDR4-RAM (U2)

QUAD SPI-NOR (U7)
Anchor
QUAD SPI-NOR (U7)
QUAD SPI-NOR (U7)

...
Anchor
eMMC Flash Memory (U21)
eMMC Flash Memory (U21)

I²C EEPROM (U13)
Anchor
I2C EEPROM (U13)
I2C EEPROM (U13)

...
Anchor
EEPROM Write Control
EEPROM Write Control

SDIO Interfaces
...
Anchor
SDIO Interfaces
SDIO Interfaces

Universal Asynchronous Interface
...
Anchor
Universal Asynchronous Interface
Universal Asynchronous Interface

USB OTG Interfaces
Anchor
USB OTG
USB OTG

...
Anchor
Ethernet
Ethernet

...
Anchor
Ethernet PHY (U4)
Ethernet PHY (U4)

Ethernet PHY Reset
Anchor
Ethernet PHY Reset
Ethernet PHY Reset

...
Anchor
MAC Address
MAC Address

RGMII Interface
Anchor
RGMII Interface
RGMII Interface

SPI Interfaces
Anchor
SPI
SPI

I²C Interface
Anchor
I2C Interface
I2C Interface

Onboard I2C Bus
...
Anchor
On

-board I2C bus
On-board I2C bus

Synchronous Audio Interface (SAI)
Anchor
Synchronous Audio Interface (SAI)
Synchronous Audio Interface (SAI)

PCI Express Interface
Anchor
PCI Express Interface
PCI Express Interface

General Purpose I/Os
...
Anchor
GPIOs
GPIOs

JTAG Interface
Anchor
JTAG Interface
JTAG Interface

...
Anchor
LVDS (Flatlink)
LVDS (Flatlink)

MIPI-Display Serial Interface 2 (MIPI-DSI2)
...
Anchor
MIPI-DSI2
MIPI-DSI2

MIPI CSI-2 Camera Interface
Anchor
MIPI CSI-2 Camera Interface
MIPI CSI-2 Camera Interface

...
Anchor
SPDIF Interface
SPDIF Interface

CPU Core Frequency Scaling
Anchor
CPU Core Frequency Scaling
CPU Core Frequency Scaling

phyCORE-i.MX 8M Mini Power Consumption
Anchor
phyCORE-i.MX 8M MINI Power Consumption
phyCORE-i.MX 8M MINI Power Consumption

Power Modes
...
Anchor
Product Temperature Grades
Product Temperature Grades

Product Temperature Grades
Anchor

phyCORE-i.MX 8M Mini BGA Mounting
Anchor
BGA Mounting
BGA Mounting

Integrating the phyCORE-i.MX 8M Mini
...
Anchor
Intergrating
Intergrating

.MX 8M Mini
...
Anchor
Handling the phyCORE-i.MX 8M Mini
Handling the phyCORE-i

phyCORE-i.MX 8M Mini on the phyBOARD-Polis
Anchor
Polis Intro
Polis Intro

Hardware Overview
...
Anchor
Hardware Overview
Hardware Overview

Polis Concept
...
Anchor
phyBOARD-Polis Concept

SBCplus Concept ...
Anchor
SBCplus Concept
SBCplus Concept

...
Anchor
phyBOARD-Polis Features
phyBOARD-Polis Features

...
Scroll Title
anchor phyBOARD-Polis Block Diagram
title phyBOARD-Polis Block Diagram
...

phyBOARD-Polis Component Overview
Anchor
phyBOARD-Polis Components
phyBOARD-Polis Components

Connectors and Pin Headers
Anchor
Connectors and Pin Headers
Connectors and Pin Headers

...
Anchor
phyBOARD-Polis Switches
phyBOARD-Polis Switches

Jumpers
...
Anchor
Jumpers
Jumpers

phyBOARD-Polis SBC Component Details
Anchor
phyBOARD-Polis SBC Component Details
phyBOARD-Polis SBC Component Details