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The table below lists the recommended components to use in the implementation of this design. The reference designators used are based on the schematic shown in Figure 1.

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This circuit will be powered by the main 3.3V rail (labeled VCC_3V3_IN on the AM57x SOM). The circuit consists of an RC delay stage, a Schmitt trigger stage, and an RC + FET circuit to generate the X_PWRON pulse.

The RC delay provides control over the X_PWRON delay. R3 and C2 can be tuned to ensure that the VCC_3V3 rail is powered and stable long enough before toggling X_PWRON. The D1 diode is included to discharge C2 quickly after VCC_3V3 is powered off. This ensures that C2 will be discharged even in the event of a quick power cycle, keeping the RC delay consistent between power cycles. Without this diode C2 may only discharge slightly before power is reapplied, which could cause a shorter delay (or even no delay at all). 

The Schmitt trigger stage is intended to prevent noise on the VCC_3V3 rail from triggering the X_PWRON transition. If the input to the Schmitt trigger is 'bouncing' around or noisy, it will filter this out and only transition X_PWRON when a significant change in the input occurs.

The third stage is implemented to generate the X_PWRON pulse low at the rising edge of the Schmitt trigger output. By gating the M1 NMOS with this RC combination, the X_PWRON will toggle low then high only once (rather than remaining low after toggling). D2 is used to clamp the negative voltage caused by the falling edge of the Schmitt trigger output. During quick power cycles this could prevent the C1 capacitor from charging up to a level that will properly bias the M1 FET. Therefore D2 is recommended for consistent behaviour during quick power cycles. An additional RC delay is added before the gate of the NMOS to slow down the switching time of the FET. This timing can be adjusted to prevent overshoot and other undesired behavior caused by the fast transitions at the gate of the FET. 

LTspice Simulation

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Figure 3 below shows how the circuit was simulated in LTspice. The 3.3V supply was driven by a pulse source to simulate a quick power cycle. A number of waveforms were captured to test the general behavior and response of the design and to verify its stability. The processor and PMIC datasheets do not seem to provide a specific amount of time that the 3.3V rail should be powered up before toggling X_PWRON. However, these timings can be adjusted by the passive components as described in the Schematic Design section if issues arise during testing and validation.

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Figure 3: Simulation Circuit Example

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Figure 4: VCC_3V3 vs. X_PWRON

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Figure 5 and 6 show the response of the RC delay with and without the D1 diode. Implementing D1 allows the C2 capacitor to discharge faster when 3V3 is powered off. When power is re-applied quickly, the RC delay circuit will then maintain a delay much closer to its expected delay value as C2 will not be starting partially charged. Note that even with D1 it is possible that C2 does not completely discharge when 3.3V power is applied immediately (though discharging is still improved). 

Figure 5: RC Delay Quick Power Cycle without D1

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Figure 6: RC Delay Quick Power Cycle with D1

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Figure 7 and 8 show the response of the FET gate input with and without the D2 diode. The R1 and C1 circuit is intended to trigger on the rising edge of the 3.3V rail, however on the falling edge it will drive a negative voltage at its output. This undesired response can be reduced by clamping the output with D2. Without D2 (during a fast power cycle) the negative voltage will cause the signal to rise to its positive level much slower as the C1 charge reverses. If the power cycle is fast enough this can prevent the M1 FET from being properly biased, and therefore not trigger X_PWRON as expected. 

Figure 7: R1/C1 Output without D2

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Figure 9 and 10 show the response of X_PWRON with and without an additional RC delay at the FET's gate input. Without this RC delay it seems the switching of the M1 NMOS is too fast, which is causing spikes on X_PWRON during the edge transitions of the gate input. By adding a small RC delay, the switching time can be slowed down so that X_PWRON does not experience these signal spikes. 

Figure 9: R1/C1 Output without RC delay

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Figure 11 shows the response of X_PWRON when the power is cycled during the low pulse of X_PWRON.The circuit behaves properly except for a small spike after the first falling edge of X_PWRON. This is likely due to the 3.3V rail being powered off quickly, which causes the FET to 'switch off' sooner. This then causes X_PWRON to follow VCC_3V3 (via the pull-up), which is still discharging towards 0V. This should not be an issue, but if this behavior is not desired the R2/C3 delay can be adjusted so that the transition at the M1 gate is slower. For example, Figure 12 shows the response when R2 is replaced with a 30k ohm resistor (this X_PWRON spike is no longer present). 

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This circuit was implemented on a PHYTEC GPIO Expansion Board to test the actual behavior of the design.

The following two figures show the response of X_PWRON at power up. This output is NOT yet connected to the X_PWRON signal on the AM5 kit to first verify the design functionality. 

Figure 13: X_PWRON Response Isolated from AM5

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After verifying the circuit produces the correct X_PWRON response, this output was connected to the X_PWRON signal on the AM5 kit. With the circuit driving X_PWRON and the current timings, the board does not boot consistently. It seems the time between VCC_3V3 stabilizing and X_PWRON toggling low is not long enough. This was adjusted by replacing R3 with a 55k resistor (rather than a 10k), and resulted in consistent booting. The new timing is shown in the following figures.  

Figure 15: X_PWRON Low Delay with R3=55k

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Figure 16: X_PWRON Toggle Delay after VCC_3V3

These passive values may need to be adjusted further to optimize the timing and behavior. 

Figure 17: FET Gate Input Response to Quick Poweroff

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Figure 18: X_PWRON vs R1/C1 Response 

A quick power cycle was implemented to analyze the behavior of the circuit under this condition. As shown in Figure 18, the response of the R1/C1 stage has a small positive spike before its typical rise response. To debug the root cause of this, the Schmitt trigger stage was further analyzed during a quick power cycle. Figure 20 shows the Schmitt trigger response at initial power up after the board has remained off for some time. However, when power is then quickly cycled after being powered up, the Schmitt trigger output has a small, positive spike as shown in Figure 21. This is likely due to the slower fall time of the VCC_3V3 rail at power off. Looking into the SN74LVC1G17 Schmiit Trigger datasheet it was found that the minimum recommended operating voltage is 1.65V. As shown in Figure 20, once VCC_3V3 approximately reaches this 1.65V, the Schmitt output is driven low and then responds as expected. Since the VCC_3V3 rail has not fallen to 0V at this point, there is some voltage remaining at the Schmitt input. It seems that with a non-zero voltage at the input while operating under 1.65V, the Schmitt trigger is in an undefined state and could have a much smaller or unpredictable positive-going input threshold voltage.  

Figure 19: X_PWRON vs R1/C1 Response During Quick Power Cycle

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The quick power cycle case does not seem to impact the intended response of the circuit however. As shown in Figure 22, the R2/C3 delay prevents this spike from rising to a level to bias the FET and drive X_PWRON low too early. So these passive values could be adjusted if necessary. However, if this is undesired, it may be resolved by implementing a method for draining VCC_3V3 faster.

Figure 22 : FET Input Response to Quick Power Cycle Spike

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X_PWRON should at least be delayed long enough for the device to arrive in the OFF state, so a power-up event is recognized properly. With R3 = 55k, the current delay is measured around ~4 ms using real components. It is recommended that R3 be increased even further to provide a safer delay margin. Replacing R3 with a 143k resistor, the delay was measured as ~10 ms. It is recommended to use a 143k resistor for R3.