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Information on this Manual

This hardware manual describes the PCM-070 System on Module, referred to as phyCORE®-i.MX 8M Plus, and the PBA-C-17, referred to as phyBOARD®-Pollux. This manual also specifies the phyCORE-i.MX 8M Plus and phyBOARD-Pollux' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Plus microcontrollers can be found in the i.MX 8M Plus Microcontroller Data Sheet/Reference Manual.

There will be several changes and additions to this manual. New versions will be released in the future with no notice. Please make sure that you are using the latest version of this manual when working with your product.

Direct Solder Connection

PHYTEC produces a Direct Solder Connection (DSC) version of the phyCORE-i.MX 8M Plus SOM (PCL-070). PHYTEC uses a Direct Solder Connection Technology (DSC) for soldering SOMs directly onto the carrier board PCB. 

The “Direct Solder Connect” of the SOM to carrier board eliminates costly PCB to PCB connectors, thereby reducing the board height. The DSC technology has an improved heat connection to the Carrier Board. It is characterized by high mechanical strength and adheres to standard norms such as those needed for railroad applications.

Information on the DSC version of the phyCORE-i.MX 8M Plus is highlighted in bold green. Please ensure you are using the correct information when working with your board.

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head. Be aware that not all components need to be considered when designing your own carrier board.

Preface

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Preface Preface

As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 8M Plus is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64-bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE PCM-070 has the following structure:

The part numbering for the DSC module of the phyCORE PCL-070 is following the same numbering schema.

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-plus/
or
https://www.phytec.com/product/phycore-i-mx-8m-plus/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Plus

PHYTEC System on Modules are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

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PCM PCM

With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in cases of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

These manuals and more can be found in the download section of phyCORE-i.MX 8M Plus Product page.

Conversions, Abbreviations, and Acronyms

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe all settings show the default position in bold, blue text.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

phyCORE-i.MX 8M Plus Introduction

The phyCORE‑i.MX 8M Plus belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Plus is a subminiature (40 mm x 37 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 8M Plus microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch, or surface mount technology (SMT 1.27 mm grid) connectors (all pitch 0.5 mm) aligning two sides of the board, allowing it to be plugged or soldered into any target application like a "big chip".

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Plus. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Plus.

phyCORE-i.MX 8M Plus Features

The phyCORE‑i.MX 8M Plus offers the following features:

• Insert-ready, sub-miniature (40 mm x 37 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Mounted using Samtec Connectors or using Direct Solder Connector (DSC)
• Populated with the NXP® Semiconductor i.MX 8M Plus microcontroller (BGA548 packaging)
• Up to 4 ARM-A53 cores (clock frequency up to 1.8 GHz)
• Machine Learning Neuronal Processing Unit (NPU) with 2.3 TOPS
• 1x Cortex M7 core (800 MHz). All Cortex M7 dedicated interfaces are explicitly made available on the SOM connector.
• Tensilica Hifi4 Audio DSP (800 MHz)
• 3D GPU GC7000UL and 2D GPU GC520L
• Neural Network Accelerator (up to 2.3TOPS)
• Onboard Image Signal Processor (up to 12MP resolution/ up to 375MP/s)
• Boot from different memory devices (eMMC Flash standard)
• Single supply voltage of +3.3 V with onboard power management
• Selectable IO voltage between 1.8 V and 3.3 V
• All controller-required supplies are generated onboard using sophisticated onboard Power Management
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• up to 8 GB

  Single cite
  citeID 1
  The maximum memory size is listed as of the printing of this manual. Please contact PHYTEC for more information about additional or new module configurations available.

  LPDDR4 RAM

• up to 64 GB

  Single cite short
  citeID 1

  onboard eMMC in the commercial temperature range (up to 32 GB for I-Temp)
• up to 64 MB

  Single cite short
  citeID 1

  Quad SPI Nor Flash
• 4kB

  Single cite short
  citeID 1

  I²C EEPROM
• 2x USB 3.0/2.0 Dual-Role interfaces with PHY
  

• 2x 1Gbit Ethernet interfaces with TSN support (either one of them with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; the second as RGMII Signals at logic-level at the signal pins instead)

• 3x I²C interfaces
  
• 2x SPI interfaces
• 1x PCIe interface
• 4x UART interfaces
• 2x CAN-FD interfaces
• 4x PWM outputs
• 1x MIPI DSI-2 interface
• 1x HDMI interface
• 2x MIPI CSI-2 camera interfaces
• 1x LVDS Tx interface 2 channels x4
• 1x 4-bit SD-Card interface
• 1x 8-bit SDIO interface
  
• 2x SAI audio interfaces
• 1x SPDIF interface
• Extreme Low Power RTC Module
• 4x temperature sensors to monitor the board's temperature profile
• All processor interfaces available at the SOM Connector
• Available for different temperature grades (see L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)

phyCORE-i.MX 8M Plus Block Diagram

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phyCORE-i.MX 8M Block Diagram phyCORE-i.MX 8M Block Diagram

phyCORE-i.MX 8M Plus Component Placement

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phyCORE-i.MX 8M Plus Component Placement phyCORE-i.MX 8M Plus Component Placement

phyCORE-i.MX 8M Plus Minimum Operating Requirements

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phyCORE-i.MX 8M Plus Minimum Operating Requirements phyCORE-i.MX 8M Plus Minimum Operating Requirements

Before the phyCORE-i.MX 8M plus can be used, please make sure the host system meets the minimum operating requirements. These include:

• The stable and clean input power supply of 3.3 V with low ESR bulk capacitors (e.g. 2x 100µ/6.3V MLCC) paired with some HF blocking capacitors (e.g. 100nF MLCC) connected to the input pins as near as possible (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)
• Appropriate configuration of the I/O voltage (3.3 V or 1.8 V) configured by signal X_VIO_Ctrl (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)
• Supply voltage for externally connected peripherals should be controlled by signal X_nPWR_READY to avoid reverse currents (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)
• If external peripherals need a longer reset delay, hold reset signal X_POR_B_VIO as long low as needed (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)
• Desired boot configuration - default configuration is "Boot from onboard eMMC" (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)
• To back up the onboard I2C-RTC, connect a buffer voltage source to input pin VBAT (L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head, L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head)

Pin Description

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Pin Description Pin Description

All controller signals extend to surface mount technology (SMT) connectors (0.5 mm). These connectors line two sides of the module (referred to as phyCORE-Connectors). This enables phyCORE-i.MX 8 Plus to be plugged into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Plus Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 8M Plus and the carrier board phyBOARD-Pollux, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the phyCORE-i.MX 8M Plus Pinout Table.

Jumpers

The phyCORE-i.MX 8M Plus (PCM-070) has only one pre-configured solder jumper (J1) meanwhile the DSC variant PCL-070 is jumperless. There are, however, a few jumpers on the phyCORE-Pollux. Information on these jumpers can be found in Jumpers.

The jumpers (J = solder jumper) have the following functions.

Power

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Power Power

The phyCORE‑i.MX 8M Plus operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 8M Plus Connector X1 in detail.

Primary System Power (VIN_3V3)

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Primary System Power (VDD_IN_3V3) Primary System Power (VDD_IN_3V3)

The phyCORE‑i.MX 8M Plus is powered by a primary voltage supply with a nominal value of +3.3 V. Onboard switching regulators generate the voltage supplies required by the i.MX 8M Plus MCU and onboard components from the primary 3.3 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M Plus must be supplied with a voltage source of 3.2...3.5 V with a maximum power consumption of a 4 A load at the VCC pins on the phyCORE.

                VIN_3V3:                        X1 → C1..C4, D1..D4 (DSC B160, B161, B163, B164, B166, B167)

Connect all +3.3 V VCC input pins to your power supply and, at minimum, the matching number of GND pins.

                Corresponding GND:           X1 → C5..C7, C15, D5..D7, D13 (DSC B152, B157, B162, B165, B168, B171)

Please refer to section L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head for information on additional GND Pins located at the phyCORE i.MX 8M Plus Connector X1.

For information on various power consumption scenarios that PHYTEC has run, go to L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head.

Power Management IC (PMIC) (U3)

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Power Management IC (PMIC) (U2) Power Management IC (PMIC) (U2)

The phyCORE-i.MX 8M Plus provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Plus via the onboard I²C bus (I2C1). The I²C address of the PMIC is 0x25.

Power Domains

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Power Domains Power Domains

External voltages to supply the board:

• VIN_3V3 3.3 V main supply voltage (3.2 .. 3.5 V / max. 4A)
  
• optional: VIN_SNVS_1V8 low power supply voltage input (1.8 V ±5% / 10mA; if left open, it is provided on-board if VIN_3V3 is present)
• VBAT backup supply voltage for the on-board I2C-Bus RTC U9 (RV-3028-C7)

External Logic IO Supply Voltage

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External Logic IO Supply Voltage External Logic IO Supply Voltage

The voltage level (VDD_IO) of the phyCORE’s logic interface circuitry is VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) which is determined by the configuration input signal X_VIO_Ctrl (X1-D8). Connect X_VIO_Ctrl to the module input supply voltage VIN_3V3 to configure VDD_IO=3.3 V interface voltage level or connect it to GND to select VDD_IO=1.8 V interface voltage level.

In order to follow the power-up and power-down sequencing mandatory for the i.MX 8M Plus, external devices connected to the phyCORE interface circuitry have to be supplied by an external power supply which is controlled by the output signal X_nPWR_READY (OD driver) which is brought out at pin X1-C14. X_nPWR_READY should control the external supply voltage which is used to supply the external interface circuitry connected to the phyCORE's interfaces. X_nPWR_READY switches to GND to start the external voltage supply or to switch over a power switch. If the onboard interface voltage (VDD_IO) switches off, X_nPWR_READY is released to high impedance. To raise the signal, an external pull-up resistor (eg. 4k7) is needed. It can be connected to voltage levels up to max. 12V depending on the external power supply control signal requirement. Use of X_nPWR_READY ensures that external components are only supplied when the supply voltages of the i.MX 8M Plus is stable and avoids undefined return currents while the system is powered down.

Backup Power (VBAT / VIN_SNVS_1V8)

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Backup Power (VRTC / NVCC_SNVS) Backup Power (VRTC / NVCC_SNVS)

To back up the on-board I2C-Bus RTC U9 (RV-3028-C7), an external voltage source must be added at Pin X1-C9 (VBAT). The RTC has an extremely low backup current consumption of only 40nA (@3 V). It is also possible to supply the internal RTC and some critical registers of the i.MX 8M Plus' low power domain (NVCC_SNVS_1V8). NVCC_SNVS_1V8 can be supplied over Pin X1-C8 if VIN_3V3 is not present.

Manual Power Switch (X_OnOff)

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Manual Power Switch (X_OnOff) Manual Power Switch (X_OnOff)

The signal X_OnOff (Pin X1-D9) is used to manual switch the power of the SOM. X_OnOff signal can be left unconnected if not used. It has a weak onboard pull-up resistor against NVCC_SNVS_1V8 and is held high as long as VIN_3V3 is present or external backup voltage VIN_SNVS_1V8 is supplied. To drive the signal to GND, use an open collector driver or push button. For more information about ONOFF refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

Reset

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Reset Reset

The X_PMIC_RST_B signal (Pin X1-C11) on the phyCORE-Connector is designated as a "cold reset" input. Driving X_PMIC_RST_B to low (has weak pull-up to SNVS_1V8) will restart the system performing a complete power recycle. X_PMIC_RST_B has a 50ms debouncing circuit. This input can be used for a mechanical reset switch button. X_POR_B_VIO Signal (Pin X1-C13) can be used to prevent bootup of the i.MX 8M Plus. This can be used as a startup as described in the section Power Management IC. 

System Boot Configuration

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System Boot Configuration System Boot Configuration

Most features of the i.MX 8 Plus microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Plus after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[3:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (X_BOOT_MODE[3:0]).

Boot Mode Selection

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Boot Mode Selection Boot Mode Selection

The boot mode of the i.MX 8M Plus microcontroller is determined by the configuration of four boot mode inputs BOOT_MODE[3:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[3:0] (X1-D22, X1-D23, X1-D24, X1-D25). L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head shows the possible settings of pins X_BOOT_MODE[3:0] and the resulting boot configuration of the i.MX 8M Plus.

The X_BOOT_MODE[3,2,0] lines have 100 kΩ pull-down resistors populated (and unpopulated pull-up resistors) while X_BOOT_MODE[1] has a 4,7 kΩ pull-up resistor on the module in parallel to the internal pull-down resistors of the i.MX8 M Plus. Leaving the four pins unconnected sets the controller to boot mode 1, boot from onboard eMMC U4 memory device. The boot configuration settings can be changed by changing the populated resistors configuration on the module or by connecting configuration resistors (e.g. 4,7 kΩ pull-up) to the X_BOOT_MODE configuration signals. The pull-up resistors must be supplied by the right VDD_IO voltage level of 1.8 V or 3.3 V depending on the VDD_IO configuration (see section L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head).

The BOOT_MODE is initialized by sampling the BOOT_MODE inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register and the pins can be used for GPIO operation.

System Memory

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System Memory System Memory

The phyCORE‑i.MX 8M Plus provides three types of onboard memory:

Additionally, an I²C-EEPROM with 4 kB is mounted to every SOM. Details for each memory type used on the phyCORE‑i.MX 8M Plus are below.

LPDDR4-RAM (U1)

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LPDDR4-RAM (U3) LPDDR4-RAM (U3)

The RAM memory interface of the phyCORE‑i.MX 8M Plus supports one 32-bit LPDDR4-RAM chip (U1). The LPDDR4 memory is accessible starting at addresses 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Plus controller. Refer to the NXP Semiconductor i.MX 8M Plus Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

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eMMC Flash Memory (U4) eMMC Flash Memory (U4)

The main flash memory of the i.MX 8M Plus is eMMC and is populated at U4. The eMMC device is programmable with 1.8 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the SD3 interface of the i.MX 8M Plus.

For more information about the eMMC Flash interface, please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

I²C EEPROM (U10)

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I2C EEPROM (U6) I2C EEPROM (U6)

The phyCORE‑i.MX 8M Plus is populated with a non-volatile 4 kB I²C EEPROM at U10. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 1 on the i.MX 8M Plus. The control registers for I²C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I²C address 0x51. The EEPROM has a second address on 0x59, which is called Identification Page, and is reserved for internal PHYTEC uses only.

QSPI NOR Flash (U5)

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QSPI NOR Flash QSPI NOR Flash

The QSPI NOR Flash memory of the phyCORE-i.MX 8M Plus at U5 can be used to store configuration data or any other general-purpose data. It can also be used as a boot device and recovery boot device. The device is accessed through QSPIA SS0 on the i.MX 8 Plus. The control registers for QSPI are mapped between addresses 0x30BB 0000 and 0x30BB FFFF. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the QSPI Flash a reliable and secure solution to store the first and second-level bootloaders.

Serial Interfaces

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Serial Interfaces Serial Interfaces

The phyCORE‑i.MX 8M Plus provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

1. 1x 4-bit SDIO interface (SD2) with controlled IO voltage
   
2. 1x 8-bit SDIO interface (SD1)
   
3. 4x high-speed UARTs
4. 2x CAN-FD interfaces
5. 2x USB 3.0/2.0 Dual-Role interfaces with PHY
6. 2x 1Gbit Ethernet interfaces with TSN support (ENET1 with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; ENET0 as RGMII Signals at logic-level at the signal pins instead)
7. 3x I²C interfaces
8. 2x Serial Peripheral Interfaces (SPI)
9. 2x SAI audio interface
10. 1x SPDIF interface
11. 1x PCI Express with x1 interface
12. 2x MIPI CSI-2 camera interfaces
13. 1x MIPI DSI-2 display interface

Details for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

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SDIO Interface SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M Plus, the interface signals extend from the first and second Ultra Secured Digital (SD1 and SD2) Host controller to the phyCORE-Connector. 

The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0. The interface supports SD cards with 3.3 V and 1.8 V I/O signals.

SDIO SD2 (4-bit)

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SDIO SD2 SDIO SD2

SDIO SD2 is a 4-bit wide interface with controlled I/O voltage to support high-speed modes that require 1.8 V I/O voltage. During runtime, the I/O voltage can be switched from 3.3 V (default) to 1.8 V by the processor via GPIO signal X_PMIC_SD_VSEL/GPIO1_IO04 which controls the PMIC integrated voltage regulator. X_VDDSW_SD2 will be used exclusively to supply an external SD or MicroSD memory card. X_VDDSW_SD2 is monitored by the PMIC load switch circuit for overcurrent and short circuits. For more details, please refer to the PMIC data sheet provided by NXP.

SDIO SD1 (8-bit)

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SDIO SD1 SDIO SD1

SDIO SD1 is an 8-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 3.3 V or 1.8 V (refer to L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head).

Universal Asynchronous Interfaces (UARTs)

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Universal Asynchronous Interface Universal Asynchronous Interface

The phyCORE‑i.MX 8M Plus provides four high-speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

USB Interfaces

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USB Interfaces USB Interfaces

The phyCORE‑i.MX 8M Plus provides two USB 3.0/2.0 dual role interfaces, which support super-speed (5Bbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Ethernet Interfaces ENET0 and ENET1

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Ethernet Interface Ethernet Interface

The phyCORE‑i.MX 8M Plus provides two Ethernet Interfaces ENET0 with TSN support and ENET1. Connection of the phyCORE‑i.MX 8M Plus to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U6. It is connected to the RGMII interface of ENET1. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Additionally, the RGMII interface of ENET0, which is available on the phyCORE‑Connector, can be used to connect an external PHY. (ENET0 RGMII Interface).

ENET1 Ethernet PHY (U6)

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Ethernet PHY (U6) Ethernet PHY (U6)

With an Ethernet PHY mounted at U6, the phyCORE‑i.MX 8M Plus has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1. In Linux environment, ENET1 interface is called eth0 as it is the port with onboard PHY.

Ethernet Signal Locations of ENET1

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Ethernet Signal Locations Ethernet Signal Locations

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface ENET1 of the i.MX 8M Plus. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH_A±, ETH_B±, ETH_C±, ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals. 

Reset of the Ethernet Controller

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Software Reset of the Ethernet Controller Software Reset of the Ethernet Controller

The reset input of the Ethernet PHY at U6 is connected to the system reset POR_B.

MAC Address

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MAC Address MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Plus is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

ENET0 RGMII Interface

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RGMII Interface RGMII Interface

In order to use an external Ethernet PHY, the RGMII interface (ENET0) of the i.MX 8M Plus is brought out at phyCORE‑Connector X1. ENET0 is primarily used for TSN network operation. For that use case, an external TSN-ready ethernet switch device is used. In a Linux environment, ENET0 interface is called eth1 as it is the port with external PHY.

SPI Interface

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SPI Interface SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X1. The SPI provides one chip select signal for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M Plus has three separate modules (eCSPI1, eCSPI2, and eCSPI3) which support clock rates of up to 60 MHz. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

I²C Interface

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I2C Interface I2C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Plus contains four identical and independent Multimaster fast-mode I²C modules. The interface of 3 modules is available on the phyCORE-Connector X1. I2C1 is reserved for controlling on the SOM. 

The following table lists the I²C ports on the phyCORE-Connector:

Audio Interface

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Audio Interface Audio Interface

 The i.MX 8M Plus supports multiple audio interfaces as listed below:

I²S Audio Interface (SAI)

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I2S Audio Interface (SAI) I2S Audio Interface (SAI)

The phyCORE-i.MX 8M Plus features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X1. 

The tables below show the signal locations for each SAI and SPDIF interface.

SAI1 Interface

SAI1 is originally an 8-bit wide interface, but some of the signals are used dedicated for the Ethernet RGMII interface of ENET1, which is connected to the onboard PHY U6. 

SAI2 Interface

SAI3 Interface

SAI5 Interface

SPDIF Interface

PCI Express Interface

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PCI Express Interface PCI Express Interface

The one 1-lane PCI Express interface of the phyCORE‑i.MX 8M Plus provides PCIe Gen. 3.0 functionality which supports up to 8 GT/s operations. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Pollux) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X1 is shown below:

General Purpose I/Os

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General Purpose I/Os General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Plus. These pins are shown below:

Besides these pins, most of the i.MX 8M Plus signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

GPIO Changing I/O Voltage

I/O voltage can be configured to 3.3 V or 1.8 V. Please refer to the section L-1009e.Ax phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.2) HW Manual Head. Be aware that changing the I/O voltage alters all interfaces which are in reference to VDD_IO.

Debug Interface

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Debug Interface Debug Interface

The phyCORE‑i.MX 8M Plus is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X1 are below:

UART Debug

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UART Debug UART Debug

The default debug UART Interfaces (TTL) is UART2 for Cortex-A53 Cores and UART4 for Cortex-M7 Core. UART1 is accessible on connector X1 pins B2 (RXD) and B3 (TXD) and UART4 on pins B4 (RXD) and B5 (TXD).

For more information also refer to Universal Asynchronous Interfaces (UARTs).

Display Interfaces

High Definition Multimedia Interface (HDMI)

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High Definition Multimedia Interface (HDMI) High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M Plus is compliant with HDMI 2.0a for up to 1920x1080 at 60 Hz display resolutions. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector X1 are shown below: