phyCORE AM335 | | AM335x ZCZ |
Pin | Name | | Design Signal Pad Name | 15 x 15 BGA | Mode 0 | Mode 1 | Mode 2 | Mode 3 | Mode 4 | Mode 5 | Mode 6 | Mode 7 |
X1.A1 | X_RMII1_RXER/_MCASP1_FSX | J15 | gmii1_rxer | J15 | gmii1_rxer | rmii1_rxer | spi1_d1_mux1 | I2C1_SCL_mux0 | mcasp1_fsx_mux1 | uart5_rtsn_mux2 | uart2_txd_mux1 | gpio3[2] |
X1.A10 | X_RMII1_TXEN/_MCASP1_AXR0 | J16 | gmii1_txen | J16 | gmii1_txen | rmii1_txen | rgmii1_tctl | timer4_mux0 | mcasp1_axr0_mux1 | eQEP0_index_mux1 | mmc2_cmd_mux2 | gpio3[3] |
X1.A11 | X_RMII1_TXD0/_GPIO0_28 | K17 | gmii1_txd0 | K17 | gmii1_txd0 | rmii1_txd0 | rgmii1_td0 | mcasp1_axr2_mux0 | mcasp1_aclkr_mux0 | eQEP0B_in_mux1 | mmc1_clk_mux1 | gpio0[28] |
X1.A13 | X_RMII1_TXD1/_GPIO0_21 | K16 | gmii1_txd1 | K16 | gmii1_txd1 | rmii1_txd1 | rgmii1_td1 | mcasp1_fsr_mux1 | mcasp1_axr1_mux0 | eQEP0A_in_mux1 | mmc1_cmd_mux1 | gpio0[21] |
X1.A14 | X_MII1_COL/MCASP1_AXR2 | H16 | gmii1_col | H16 | gmii1_col | rmii2_refclk | spi1_sclk_mux1 | uart5_rxd_mux0 | mcasp1_axr2_mux1 | mmc2_dat3_mux2 | mcasp0_axr2_mux4 | gpio3[0] |
X1.A15 | X_RMII1_CRS/_MCASP1_ACLKX | H17 | gmii1_crs | H17 | gmii1_crs | rmii1_crs_dv | spi1_d0_mux1 | I2C1_SDA_mux0 | mcasp1_aclkx_mux1 | uart5_ctsn_mux2 | uart2_rxd_mux1 | gpio3[1] |
X1.A16 | X_GPMC_AD1 | V7 | gpmc_ad1 | V7 | gpmc_ad1 | mmc1_dat1_mux2 | | | | | | gpio1[1] |
X1.A23 | X_GPMC_AD0 | U7 | gpmc_ad0 | U7 | gpmc_ad0 | mmc1_dat0_mux2 | | | | | | gpio1[0] |
X1.A24 | X_GPMC_AD2 | R8 | gpmc_ad2 | R8 | gpmc_ad2 | mmc1_dat2_mux2 | | | | | | gpio1[2] |
X1.A25 | X_GPMC_AD4 | U8 | gpmc_ad4 | U8 | gpmc_ad4 | mmc1_dat4_mux2 | | | | | | gpio1[4] |
X1.A26 | X_GPMC_AD5 | V8 | gpmc_ad5 | V8 | gpmc_ad5 | mmc1_dat5_mux2 | | | | | | gpio1[5] |
X1.A28 | X_GPMC_AD3 | T8 | gpmc_ad3 | T8 | gpmc_ad3 | mmc1_dat3_mux2 | | | | | | gpio1[3] |
X1.A29 | X_GPMC_AD6 | R9 | gpmc_ad6 | R9 | gpmc_ad6 | mmc1_dat6_mux2 | | | | | | gpio1[6] |
X1.A3 | X_RMII1_RXD0/_GPIO2_21 | M16 | gmii1_rxd0 | M16 | gmii1_rxd0 | rmii1_rxd0 | rgmii1_rd0 | mcasp1_ahclkx_mux0 | mcasp1_ahclkr_mux0 | mcasp1_aclkr_mux1 | mcasp0_axr3_mux4 | gpio2[21] |
X1.A30 | X_GPMC_AD7 | T9 | gpmc_ad7 | T9 | gpmc_ad7 | mmc1_dat7_mux2 | | | | | | gpio1[7] |
X1.A33 | X_GPMC_ADVn_ALE | R7 | gpmc_advn_ale | R7 | gpmc_advn_ale | | timer4_mux3 | | | | | gpio2[2] |
X1.A34 | X_GPMC_BE0n_CLE | T6 | gpmc_be0n_cle | T6 | gpmc_be0n_cle | | timer5_mux3 | | | | | gpio2[5] |
X1.A35 | X_RGMII2_RCTL/_MMC2_DAT0/_P_MII1_TXD3 | V14 | gpmc_a1 | V14 | gpmc_a1_mux0 | gmii2_rxdv | rgmii2_rctl | mmc2_dat0_mux0 | gpmc_a17_mux0 | pr1_mii1_txd3 | ehrpwm0_synco_mux1 | gpio1[17] |
X1.A36 | X_RGMII2_TD3/_MMC2_DAT1/_P_MII1_TXD2 | U14 | gpmc_a2 | U14 | gpmc_a2_mux0 | gmii2_txd3 | rgmii2_td3 | mmc2_dat1_mux0 | gpmc_a18_mux0 | pr1_mii1_txd2 | ehrpwm1A_mux1 | gpio1[18] |
X1.A39 | X_RGMII2_TD2/_MMC2_DAT2/_P_MII1_TXD1 | T14 | gpmc_a3 | T14 | gpmc_a3_mux0 | gmii2_txd2 | rgmii2_td2 | mmc2_dat2_mux0 | gpmc_a19_mux0 | pr1_mii1_txd1 | ehrpwm1B_mux1 | gpio1[19] |
X1.A4 | X_RMII1_RXD1/_GPIO2_20 | L15 | gmii1_rxd1 | L15 | gmii1_rxd1 | rmii1_rxd1 | rgmii1_rd1 | mcasp1_axr3_mux0 | mcasp1_fsr_mux0 | eQEP0_strobe_mux1 | mmc2_clk_mux2 | gpio2[20] |
X1.A40 | X_RGMII2_TD0/_P_MII1_RXD3 | V15 | gpmc_a5 | V15 | gpmc_a5_mux0 | gmii2_txd0 | rgmii2_td0 | rmii2_txd0 | gpmc_a21_mux0 | pr1_mii1_rxd3 | eQEP1B_in_mux1 | gpio1[21] |
X1.A43 | X_RGMII2_RCLK/_MMC2_DAT5/_P_MII1_RXD1 | T15 | gpmc_a7 | T15 | gpmc_a7_mux0 | gmii2_rxclk | rgmii2_rclk | mmc2_dat5_mux0 | gpmc_a23_mux0 | pr1_mii1_rxd1 | eQEP1_strobe_mux1 | gpio1[23] |
X1.A44 | X_RGMII2_RD2/_MMC2_DAT7/_P_MII1_MR1_CLK | U16 | gpmc_a9 | U16 | gpmc_a9_mux0 | gmii2_rxd2 | rgmii2_rd2 | mmc2_dat7_mux0 | gpmc_a25_mux0 | pr1_mii_mr1_clk | mcasp0_fsx_mux3 | gpio1[25] |
X1.A45 | X_RGMII2_RD1/_P_MII1_RXDV | T16 | gpmc_a10 | T16 | gpmc_a10_mux0 | gmii2_rxd1 | rgmii2_rd1 | rmii2_rxd1 | gpmc_a26_mux0 | pr1_mii1_rxdv | mcasp0_axr0_mux3 | gpio1[26] |
X1.A46 | X_RGMII2_RD0/_P_MII1_RXER | V17 | gpmc_a11 | V17 | gpmc_a11_mux0 | gmii2_rxd0 | rgmii2_rd0 | rmii2_rxd0 | gpmc_a27_mux0 | pr1_mii1_rxer | mcasp0_axr1_mux3 | gpio1[27] |
X1.A48 | X_MMC2_CLK/_P_MDIO_MDCLK | V12 | gpmc_clk | V12 | gpmc_clk_mux0 | lcd_memory_clk_mux0 | gpmc_wait1 | mmc2_clk_mux0 | pr1_mii1_crs_mux0 | pr1_mdio_mdclk | mcasp0_fsr_mux3 | gpio2[1] |
X1.A8 | X_UART3_RX | L17 | gmii1_rxd3 | L17 | gmii1_rxd3 | uart3_rxd_mux0 | rgmii1_rd3 | mmc0_dat5 | mmc1_dat2_mux1 | uart1_dtrn_mux0 | mcasp0_axr0_mux2 | gpio2[18] |
X1.A9 | X_UART3_TX | L16 | gmii1_rxd2 | L16 | gmii1_rxd2 | uart3_txd_mux0 | rgmii1_rd2 | mmc0_dat4 | mmc1_dat3_mux1 | uart1_rin_mux0 | mcasp0_axr1_mux2 | gpio2[19] |
X1.B10 | X_TDO | A11 | TDO | A11 | TDO | | | | | | | |
X1.B11 | X_TRSTn | B10 | nTRST | B10 | nTRST | | | | | | | |
X1.B12 | X_TMS | C11 | TMS | C11 | TMS | | | | | | | |
X1.B15 | X_INTR1 | D14 | xdma_event_intr1 | D14 | xdma_event_intr1 | | tclkin | clkout2 | timer7_mux1 | pr1_pru0_pru_r31[16] | EMU3_mux0 | gpio0[20] |
X1.B17 | X_GPMC_WEn | U6 | gpmc_wen | U6 | gpmc_wen | | timer6_mux3 | | | | | gpio2[4] |
X1.B18 | X_GPIO3_8 | B14 | EMU1 | B14 | EMU1 | | | | | | | gpio3[8] |
X1.B2 | X_MDIO_DATA | M17 | mdio_data | M17 | mdio_data | timer6_mux2 | uart5_rxd_mux3 | uart3_ctsn_mux2 | mmc0_sdcd_mux2 | mmc1_cmd_mux2 | mmc2_cmd_mux1 | gpio0[0] |
X1.B20 | X_GPIO3_7 | C14 | EMU0 | C14 | EMU0 | | | | | | | gpio3[7] |
X1.B21 | X_GPMC_CS0n | V6 | gpmc_csn0 | V6 | gpmc_csn0 | | | | | | | gpio1[29] |
X1.B22 | X_GPMC_OEn_REn | T7 | gpmc_oen_ren | T7 | gpmc_oen_ren | | timer7_mux3 | | | | | gpio2[3] |
X1.B26 | X_LCD_D21 | T11 | gpmc_ad10 | T11 | gpmc_ad10 | lcd_data21 | mmc1_dat2_mux0 | mmc2_dat6_mux1 | ehrpwm2_tripzone_input_mux1 | pr1_mii0_txen_mux0 | | gpio0[26] |
X1.B27 | X_LCD_D23 | U10 | gpmc_ad8 | U10 | gpmc_ad8 | lcd_data23 | mmc1_dat0_mux0 | mmc2_dat4_mux1 | ehrpwm2A_mux1 | pr1_mii_mt0_clk_mux0 | | gpio0[22] |
X1.B28 | X_LCD_D22/_P_MII0_COL | T10 | gpmc_ad9 | T10 | gpmc_ad9 | lcd_data22 | mmc1_dat1_mux0 | mmc2_dat5_mux1 | ehrpwm2B_mux1 | pr1_mii0_col | | gpio0[23] |
X1.B3 | X_MDIO_CLK | M18 | mdio_clk | M18 | mdio_clk | timer5_mux2 | uart5_txd_mux3 | uart3_rtsn_mux2 | mmc0_sdwp_mux2 | mmc1_clk_mux2 | mmc2_clk_mux1 | gpio0[1] |
X1.B30 | X_LCD_D20 | U12 | gpmc_ad11 | U12 | gpmc_ad11 | lcd_data20 | mmc1_dat3_mux0 | mmc2_dat7_mux1 | ehrpwm0_synco_mux1 | pr1_mii0_txd3_mux0 | | gpio0[27] |
X1.B31 | X_LCD_D19 | T12 | gpmc_ad12 | T12 | gpmc_ad12 | lcd_data19 | mmc1_dat4_mux0 | mmc2_dat0_mux1 | eQEP2A_in_mux1 | pr1_mii0_txd2_mux0 | pr1_pru0_pru_r30[14] | gpio1[12] |
X1.B32 | X_LCD_D18 | R12 | gpmc_ad13 | R12 | gpmc_ad13 | lcd_data18 | mmc1_dat5_mux0 | mmc2_dat1_mux1 | eQEP2B_in_mux1 | pr1_mii0_txd1_mux0 | pr1_pru0_pru_r30[15] | gpio1[13] |
X1.B33 | X_P_MII1_TXEN | U17 | gpmc_wpn | U17 | gpmc_wpn | gmii2_rxer | gpmc_csn5 | rmii2_rxer | mmc2_sdcd_mux0 | pr1_mii1_txen | uart4_txd_mux2 | gpio0[31] |
X1.B36 | X_LCD_D16 | U13 | gpmc_ad15 | U13 | gpmc_ad15 | lcd_data16 | mmc1_dat7_mux0 | mmc2_dat3_mux1 | eQEP2_strobe_mux1 | pr1_ecap0_ecap_capin_apwm_o_mux0 | pr1_pru0_pru_r31[15] | gpio1[15] |
X1.B37 | X_RGMII2_INT/_MMC2_DAT3/_P_MII1_RXLINK | U18 | gpmc_be1n | U18 | gpmc_be1n_mux0 | gmii2_col | gpmc_csn6 | mmc2_dat3_mux0 | gpmc_dir | pr1_mii1_rxlink | mcasp0_aclkr_mux3 | gpio1[28] |
X1.B38 | X_LCD_D17 | V13 | gpmc_ad14 | V13 | gpmc_ad14 | lcd_data17 | mmc1_dat6_mux0 | mmc2_dat2_mux1 | eQEP2_index_mux1 | pr1_mii0_txd0_mux0 | pr1_pru0_pru_r31[14] | gpio1[14] |
X1.B40 | X_RGMII2_RD3/_MMC2_DAT6/_P_MII1_RXD0 | V16 | gpmc_a8 | V16 | gpmc_a8_mux0 | gmii2_rxd3 | rgmii2_rd3 | mmc2_dat6_mux0 | gpmc_a24_mux0 | pr1_mii1_rxd0 | mcasp0_aclkx_mux3 | gpio1[24] |
X1.B41 | X_RGMII2_TD1/_P_MII1_TXD0 | R14 | gpmc_a4 | R14 | gpmc_a4_mux0 | gmii2_txd1 | rgmii2_td1 | rmii2_txd1 | gpmc_a20_mux0 | pr1_mii1_txd0 | eQEP1A_in_mux1 | gpio1[20] |
X1.B42 | X_RGMII2_TCTL/_P_MII1_MT_CLK | R13 | gpmc_a0 | R13 | gpmc_a0_mux0 | gmii2_txen | rgmii2_tctl | rmii2_txen | gpmc_a16_mux0 | pr1_mii_mt1_clk | ehrpwm1_tripzone_input_mux1 | gpio1[16] |
X1.B46 | X_MMC2_CMD/_P_MDIO_DATA | T13 | gpmc_csn3 | T13 | gpmc_csn3 | | | mmc2_cmd_mux0 | pr1_mii0_crs_mux0 | pr1_mdio_data | EMU4_mux0 | gpio2[0] |
X1.B47 | X_GPIO1_30 | U9 | gpmc_csn1 | U9 | gpmc_csn1 | gpmc_clk_mux1 | mmc1_clk_mux0 | pr1_edio_data_in6_mux0 | pr1_edio_data_out6_mux0 | pr1_pru1_pru_r30[12] | pr1_pru1_pru_r31[12] | gpio1[30] |
X1.B48 | X_GPIO1_31 | V9 | gpmc_csn2 | V9 | gpmc_csn2 | gpmc_be1n_mux1 | mmc1_cmd_mux0 | pr1_edio_data_in7_mux0 | pr1_edio_data_out7_mux0 | pr1_pru1_pru_r30[13] | pr1_pru1_pru_r31[13] | gpio1[31] |
X1.B5 | X_GPIO3_18 | B12 | mcasp0_aclkr | B12 | mcasp0_aclkr_mux0 | eQEP0A_in_mux0 | mcasp0_axr2_mux1 | mcasp1_aclkx_mux2 | mmc0_sdwp_mux1 | pr1_pru0_pru_r30[4] | pr1_pru0_pru_r31[4] | gpio3[18] |
X1.B6 | X_MII1_RCTL/_GPIO3_4 | J17 | gmii1_rxdv | J17 | gmii1_rxdv | lcd_memory_clk_mux1 | rgmii1_rctl | uart5_txd_mux1 | mcasp1_aclkx_mux0 | mmc2_dat0_mux2 | mcasp0_aclkr_mux2 | gpio3[4] |
X1.B7 | X_TDI | B11 | TDI | B11 | TDI | | | | | | | |
X1.B8 | X_TCK | A12 | TCK | A12 | TCK | | | | | | | |
X3.A17 | X_SPI0_CS0 | A16 | spi0_cs0 | A16 | spi0_cs0 | mmc2_sdwp_mux0 | I2C1_SCL_mux3 | ehrpwm0_synci_mux1 | pr1_uart0_txd_mux0 | pr1_edio_data_in1 | pr1_edio_data_out1 | gpio0[5] |
X3.A18 | X_MMC0_SDCD | C15 | spi0_cs1 | C15 | spi0_cs1 | uart3_rxd_mux1 | eCAP1_in_PWM1_out_mux0 | mmc0_pow_mux1 | xdma_event_intr2_mux1 | mmc0_sdcd_mux0 | EMU4_mux1 | gpio0[6] |
X3.A19 | X_I2C0_SCL | C16 | I2C0_SCL | C16 | I2C0_SCL | timer7_mux2 | uart2_rtsn_mux0 | eCAP1_in_PWM1_out_mux2 | | | | gpio3[6] |
X3.A20 | X_I2C0_SDA | C17 | I2C0_SDA | C17 | I2C0_SDA | timer4_mux2 | uart2_ctsn_mux0 | eCAP2_in_PWM2_out_mux2 | | | | gpio3[5] |
X3.A22 | X_MCASP0_AXR0 | D12 | mcasp0_axr0 | D12 | mcasp0_axr0_mux0 | ehrpwm0_tripzone_input_mux0 | | spi1_d1_mux2 | mmc2_sdcd_mux1 | pr1_pru0_pru_r30[2] | pr1_pru0_pru_r31[2] | gpio3[16] |
X3.A23 | X_GPIO3_17 | C12 | mcasp0_ahclkr | C12 | mcasp0_ahclkr_mux0 | ehrpwm0_synci_mux0 | mcasp0_axr2_mux0 | spi1_cs0_mux4 | eCAP2_in_PWM2_out_mux1 | pr1_pru0_pru_r30[3] | pr1_pru0_pru_r31[3] | gpio3[17] |
X3.A24 | X_DCAN0_RX | K15 | gmii1_txd2 | K15 | gmii1_txd2 | dcan0_rx_mux0 | rgmii1_td2 | uart4_txd_mux0 | mcasp1_axr0_mux0 | mmc2_dat2_mux2 | mcasp0_ahclkx_mux2 | gpio0[17] |
X3.A25 | X_DCAN0_TX | J18 | gmii1_txd3 | J18 | gmii1_txd3 | dcan0_tx_mux0 | rgmii1_td3 | uart4_rxd_mux0 | mcasp1_fsx_mux0 | mmc2_dat1_mux2 | mcasp0_fsr_mux2 | gpio0[16] |
X3.A27 | X_MCASP0_AHCLKX | A14 | mcasp0_ahclkx | A14 | mcasp0_ahclkx_mux0 | eQEP0_strobe_mux0 | mcasp0_axr3_mux0 | mcasp1_axr1_mux1 | EMU4_mux2 | pr1_pru0_pru_r30[7] | pr1_pru0_pru_r31[7] | gpio3[21] |
X3.A28 | X_MCASP0_AXR1 | D13 | mcasp0_axr1 | D13 | mcasp0_axr1_mux0 | eQEP0_index_mux0 | | mcasp1_axr0_mux2 | EMU3_mux2 | pr1_pru0_pru_r30[6] | pr1_pru0_pru_r31[6] | gpio3[20] |
X3.A29 | X_MCASP0_FSX | B13 | mcasp0_fsx | B13 | mcasp0_fsx_mux0 | ehrpwm0B_mux0 | | spi1_d0_mux2 | mmc1_sdcd_mux1 | pr1_pru0_pru_r30[1] | pr1_pru0_pru_r31[1] | gpio3[15] |
X3.A30 | X_PORZ | B15 | porz | B15 | porz | | | | | | | |
X3.A32 | X_UART0_TXD | E16 | uart0_txd | E16 | uart0_txd | spi1_cs1_mux3 | dcan0_rx_mux1 | I2C2_SCL_mux1 | eCAP1_in_PWM1_out_mux1 | pr1_pru1_pru_r30[15] | pr1_pru1_pru_r31[15] | gpio1[11] |
X3.A33 | X_UART0_RXD | E15 | uart0_rxd | E15 | uart0_rxd | spi1_cs0_mux3 | dcan0_tx_mux1 | I2C2_SDA_mux1 | eCAP2_in_PWM2_out_mux0 | pr1_pru1_pru_r30[14] | pr1_pru1_pru_r31[14] | gpio1[10] |
X3.A34 | X_SPI0_D0 | B17 | spi0_d0 | B17 | spi0_d0 | uart2_txd_mux3 | I2C2_SCL_mux2 | ehrpwm0B_mux1 | pr1_uart0_rts_n_mux0 | pr1_edio_latch_in | EMU3_mux1 | gpio0[3] |
X3.A35 | X_SPI0_D1 | B16 | spi0_d1 | B16 | spi0_d1 | mmc1_sdwp_mux0 | I2C1_SDA_mux3 | ehrpwm0_tripzone_input_mux1 | pr1_uart0_rxd_mux0 | pr1_edio_data_in0 | pr1_edio_data_out0 | gpio0[4] |
X3.A37 | X_LCD_D3/_P_MII0_TXD2 | R4 | lcd_data3 | R4 | lcd_data3 | gpmc_a3_mux1 | pr1_mii0_txd2_mux1 | ehrpwm0_synco_mux0 | | pr1_pru1_pru_r30[3] | pr1_pru1_pru_r31[3] | gpio2[9] |
X3.A38 | X_LCD_D2/_P_MII0_TXD3 | R3 | lcd_data2 | R3 | lcd_data2 | gpmc_a2_mux1 | pr1_mii0_txd3_mux1 | ehrpwm2_tripzone_input_mux0 | | pr1_pru1_pru_r30[2] | pr1_pru1_pru_r31[2] | gpio2[8] |
X3.A39 | X_LCD_D4/_P_MII0_TXD1 | T1 | lcd_data4 | T1 | lcd_data4 | gpmc_a4_mux1 | pr1_mii0_txd1_mux1 | eQEP2A_in_mux0 | | pr1_pru1_pru_r30[4] | pr1_pru1_pru_r31[4] | gpio2[10] |
X3.A40 | X_LCD_D5/_P_MII0_TXD0 | T2 | lcd_data5 | T2 | lcd_data5 | gpmc_a5_mux1 | pr1_mii0_txd0_mux1 | eQEP2B_in_mux0 | | pr1_pru1_pru_r30[5] | pr1_pru1_pru_r31[5] | gpio2[11] |
X3.A42 | X_LCD_D0/_P_MII0_MT_CLK | R1 | lcd_data0 | R1 | lcd_data0 | gpmc_a0_mux1 | pr1_mii_mt0_clk_mux1 | ehrpwm2A_mux0 | | pr1_pru1_pru_r30[0] | pr1_pru1_pru_r31[0] | gpio2[6] |
X3.A43 | X_LCD_D1/_P_MII0_TXEN | R2 | lcd_data1 | R2 | lcd_data1 | gpmc_a1_mux1 | pr1_mii0_txen_mux1 | ehrpwm2B_mux0 | | pr1_pru1_pru_r30[1] | pr1_pru1_pru_r31[1] | gpio2[7] |
X3.A44 | X_LCD_D13/_P_MII0_RXER | V3 | lcd_data13 | V3 | lcd_data13 | gpmc_a17_mux1 | eQEP1B_in_mux0 | mcasp0_fsr_mux1 | mcasp0_axr3_mux3 | pr1_mii0_rxer | uart4_rtsn_mux1 | gpio0[9] |
X3.A45 | X_LCD_HSYNC | R5 | lcd_hsync | R5 | lcd_hsync | gpmc_a9_mux1 | | pr1_edio_data_in3 | pr1_edio_data_out3 | pr1_pru1_pru_r30[9] | pr1_pru1_pru_r31[9] | gpio2[23] |
X3.A47 | X_USB0_DM | N18 | USB0_DM | N18 | USB0_DM | | | | | | | |
X3.A48 | X_USB0_DP | N17 | USB0_DP | N17 | USB0_DP | | | | | | | |
X3.A49 | X_LCD_D12/_P_MII0_RXLINK | V2 | lcd_data12 | V2 | lcd_data12 | gpmc_a16_mux1 | eQEP1A_in_mux0 | mcasp0_aclkr_mux1 | mcasp0_axr2_mux3 | pr1_mii0_rxlink | uart4_ctsn_mux1 | gpio0[8] |
X3.A5 | X_AM335_NMIn | B18 | nNMI | B18 | nNMI | | | | | | | |
X3.A50 | X_LCD_AC_BIAS_EN_/P_MII1_CRS | R6 | lcd_ac_bias_en | R6 | lcd_ac_bias_en | gpmc_a11_mux1 | pr1_mii1_crs_mux1 | pr1_edio_data_in5 | pr1_edio_data_out5 | pr1_pru1_pru_r30[11] | pr1_pru1_pru_r31[11] | gpio2[25] |
X3.A52 | X_LCD_D8/_P_MII0_RXD3 | U1 | lcd_data8 | U1 | lcd_data8 | gpmc_a12_mux0 | ehrpwm1_tripzone_input_mux0 | mcasp0_aclkx_mux1 | uart5_txd_mux2 | pr1_mii0_rxd3 | uart2_ctsn_mux1 | gpio2[14] |
X3.A53 | X_LCD_D14/_P_MII0_MR_CLK | V4 | lcd_data14 | V4 | lcd_data14 | gpmc_a18_mux1 | eQEP1_index_mux0 | mcasp0_axr1_mux1 | uart5_rxd_mux1 | pr1_mii_mr0_clk | uart5_ctsn_mux1 | gpio0[10] |
X3.A54 | X_LCD_D15/_P_MII0_RXDV | T5 | lcd_data15 | T5 | lcd_data15 | gpmc_a19_mux1 | eQEP1_strobe_mux0 | mcasp0_ahclkx_mux1 | mcasp0_axr3_mux2 | pr1_mii0_rxdv | uart5_rtsn_mux1 | gpio0[11] |
X3.A55 | X_LCD_D6 | T3 | lcd_data6 | T3 | lcd_data6 | gpmc_a6_mux1 | pr1_edio_data_in6_mux1 | eQEP2_index_mux0 | pr1_edio_data_out6_mux1 | pr1_pru1_pru_r30[6] | pr1_pru1_pru_r31[6] | gpio2[12] |
X3.A57 | X_LCD_D7 | T4 | lcd_data7 | T4 | lcd_data7 | gpmc_a7_mux1 | pr1_edio_data_in7_mux1 | eQEP2_strobe_mux0 | pr1_edio_data_out7_mux1 | pr1_pru1_pru_r30[7] | pr1_pru1_pru_r31[7] | gpio2[13] |
X3.A58 | X_LCD_D9/_P_MII0_RXD2 | U2 | lcd_data9 | U2 | lcd_data9 | gpmc_a13_mux0 | ehrpwm0_synco_mux0 | mcasp0_fsx_mux1 | uart5_rxd_mux2 | pr1_mii0_rxd2 | uart2_rtsn_mux1 | gpio2[15] |
X3.A59 | X_LCD_D10/_P_MII0_RXD1 | U3 | lcd_data10 | U3 | lcd_data10 | gpmc_a14_mux0 | ehrpwm1A_mux0 | mcasp0_axr0_mux1 | | pr1_mii0_rxd1 | uart3_ctsn_mux1 | gpio2[16] |
X3.A60 | X_UART2_RX | K18 | gmii1_txclk | K18 | gmii1_txclk | uart2_rxd_mux0 | rgmii1_tclk | mmc0_dat7 | mmc1_dat0_mux1 | uart1_dcdn_mux0 | mcasp0_aclkx_mux2 | gpio3[9] |
X3.B10 | X_UART1_TXD/_P_UART0_TXD | D15 | uart1_txd | D15 | uart1_txd | mmc2_sdwp_mux1 | dcan1_rx_mux1 | I2C1_SCL_mux2 | | pr1_uart0_txd_mux1 | pr1_pru0_pru_r31[16] | gpio0[15] |
X3.B11 | X_UART1_RXD/_P_UART0_RXD | D16 | uart1_rxd | D16 | uart1_rxd | mmc1_sdwp_mux1 | dcan1_tx_mux1 | I2C1_SDA_mux2 | | pr1_uart0_rxd_mux1 | pr1_pru1_pru_r31[16] | gpio0[14] |
X3.B13 | X_RESET_OUTn | A10 | nRESETIN_OUT | A10 | nRESETIN_OUT | | | | | | | |
X3.B15 | X_GPIO_3_19 | C13 | mcasp0_fsr | C13 | mcasp0_fsr_mux0 | eQEP0B_in_mux0 | mcasp0_axr3_mux1 | mcasp1_fsx_mux2 | EMU2_mux2 | pr1_pru0_pru_r30[5] | pr1_pru0_pru_r31[5] | gpio3[19] |
X3.B16 | X_MCASP0_ACLKX | A13 | mcasp0_aclkx | A13 | mcasp0_aclkx_mux0 | ehrpwm0A_mux0 | | spi1_sclk_mux2 | mmc0_sdcd_mux1 | pr1_pru0_pru_r30[0] | pr1_pru0_pru_r31[0] | gpio3[14] |
X3.B18 | X_USB1_DP | R17 | USB1_DP | R17 | USB1_DP | | | | | | | |
X3.B19 | X_USB1_DM | R18 | USB1_DM | R18 | USB1_DM | | | | | | | |
X3.B21 | X_USB1_DRVVBUS | F15 | USB1_DRVVBUS | F15 | USB1_DRVVBUS | | | | | | | gpio3[13] |
X3.B23 | X_USB1_ID | P17 | USB1_ID | P17 | USB1_ID | | | | | | | |
X3.B24 | X_USB1_CE | P18 | USB1_CE | P18 | USB1_CE | | | | | | | |
X3.B26 | X_ECAP0_IN_PWM0_OUT | C18 | eCAP0_in_PWM0_out | C18 | eCAP0_in_PWM0_out | uart3_txd_mux1 | spi1_cs1_mux1 | pr1_ecap0_ecap_capin_apwm_o_mux1 | spi1_sclk_mux0 | mmc0_sdwp_mux0 | xdma_event_intr2_mux2 | gpio0[7] |
X3.B28 | X_AIN7 | C9 | AIN7 | C9 | AIN7 | | | | | | | |
X3.B29 | X_AIN6 | A8 | AIN6 | A8 | AIN6 | | | | | | | |
X3.B31 | X_AIN5 | B8 | AIN5 | B8 | AIN5 | | | | | | | |
X3.B32 | X_AIN4 | C8 | AIN4 | C8 | AIN4 | | | | | | | |
X3.B34 | X_AIN2 | B7 | AIN2 | B7 | AIN2 | | | | | | | |
X3.B35 | X_AIN3 | A7 | AIN3 | A7 | AIN3 | | | | | | | |
X3.B37 | X_AIN1 | C7 | AIN1 | C7 | AIN1 | | | | | | | |
X3.B38 | X_AIN0 | B6 | AIN0 | B6 | AIN0 | | | | | | | |
X3.B39 | X_AM335_EXT_WAKEUP | C5 | EXT_WAKEUP | C5 | EXT_WAKEUP | | | | | | | |
X3.B42 | X_USB0_DRVVBUS | F16 | USB0_DRVVBUS | F16 | USB0_DRVVBUS | | | | | | | gpio0[18] |
X3.B43 | X_USB0_ID | P16 | USB0_ID | P16 | USB0_ID | | | | | | | |
X3.B44 | X_USB0_CE | M15 | USB0_CE | M15 | USB0_CE | | | | | | | |
X3.B47 | X_LCD_VSYNC | U5 | lcd_vsync | U5 | lcd_vsync | gpmc_a8_mux1 | | pr1_edio_data_in2 | pr1_edio_data_out2 | pr1_pru1_pru_r30[8] | pr1_pru1_pru_r31[8] | gpio2[22] |
X3.B49 | X_LCD_D11/_P_MII0_RXD0 | U4 | lcd_data11 | U4 | lcd_data11 | gpmc_a15_mux0 | ehrpwm1B_mux0 | mcasp0_ahclkr_mux1 | mcasp0_axr2_mux2 | pr1_mii0_rxd0 | uart3_rtsn_mux1 | gpio2[17] |
X3.B50 | X_GPIO1_9 | E17 | uart0_rtsn | E17 | uart0_rtsn | uart4_txd_mux1 | dcan1_rx_mux0 | I2C1_SCL_mux1 | spi1_d1_mux0 | spi1_cs0_mux2 | pr1_edc_sync1_out | gpio1[9] |
X3.B51 | X_GPIO1_8 | E18 | uart0_ctsn | E18 | uart0_ctsn | uart4_rxd_mux1 | dcan1_tx_mux0 | I2C1_SDA_mux1 | spi1_d0_mux0 | timer7_mux0 | pr1_edc_sync0_out | gpio1[8] |
X3.B54 | X_MMC0_CMD | G18 | mmc0_cmd | G18 | mmc0_cmd | gpmc_a25_mux1 | uart3_rtsn_mux0 | uart2_txd_mux2 | dcan1_rx_mux2 | pr1_pru0_pru_r30[13] | pr1_pru0_pru_r31[13] | gpio2[31] |
X3.B55 | X_MMC0_D0 | G16 | mmc0_dat0 | G16 | mmc0_dat0 | gpmc_a23_mux1 | uart5_rtsn_mux0 | uart3_txd_mux2 | uart1_rin_mux1 | pr1_pru0_pru_r30[11] | pr1_pru0_pru_r31[11] | gpio2[29] |
X3.B56 | X_MMC0_D1 | G15 | mmc0_dat1 | G15 | mmc0_dat1 | gpmc_a22_mux1 | uart5_ctsn_mux0 | uart3_rxd_mux2 | uart1_dtrn_mux1 | pr1_pru0_pru_r30[10] | pr1_pru0_pru_r31[10] | gpio2[28] |
X3.B58 | X_MMC0_D2 | F18 | mmc0_dat2 | F18 | mmc0_dat2 | gpmc_a21_mux1 | uart4_rtsn_mux0 | timer6_mux0 | uart1_dsrn_mux1 | pr1_pru0_pru_r30[9] | pr1_pru0_pru_r31[9] | gpio2[27] |
X3.B59 | X_MMC0_D3 | F17 | mmc0_dat3 | F17 | mmc0_dat3 | gpmc_a20_mux1 | uart4_ctsn_mux0 | timer5_mux0 | uart1_dcdn_mux1 | pr1_pru0_pru_r30[8] | pr1_pru0_pru_r31[8] | gpio2[26] |
X3.B60 | X_UART2_TX | L18 | gmii1_rxclk | L18 | gmii1_rxclk | uart2_txd_mux0 | rgmii1_rclk | mmc0_dat6 | mmc1_dat1_mux1 | uart1_dsrn_mux0 | mcasp0_fsx_mux2 | gpio3[10] |
X3.B8 | X_UART1_CTS | D18 | uart1_ctsn | D18 | uart1_ctsn | timer6_mux1 | dcan0_tx_mux2 | I2C2_SDA_mux0 | spi1_cs0_mux0 | pr1_uart0_cts_n_mux1 | pr1_edc_latch0_in | gpio0[12] |
X3.B9 | X_UART1_RTS | D17 | uart1_rtsn | D17 | uart1_rtsn | timer5_mux1 | dcan0_rx_mux2 | I2C2_SCL_mux0 | spi1_cs1_mux0 | pr1_uart0_rts_n_mux1 | pr1_edc_latch1_in | gpio0[13] |
X1.B45 | X_CLKOUT1 | A15 | xdma_event_intr0 | A15 | xdma_event_intr0 | | timer4_mux1 | clkout1 | spi1_cs1_mux2 | pr1_pru1_pru_r31[16] | EMU2_mux0 | gpio0[19] |
X3.A15 | X_SPIO0_SCLK | A17 | spi0_sclk | A17 | spi0_sclk | uart2_rxd_mux3 | I2C2_SDA_mux2 | ehrpwm0A_mux1 | pr1_uart0_cts_n_mux0 | pr1_edio_sof | EMU2_mux1 | gpio0[2] |
| | A3 | testout | A3 | testout | | | | | | | |
| | A4 | OSC1_OUT | A4 | OSC1_OUT | | | | | | | |
| | A6 | OSC1_IN | A6 | OSC1_IN | | | | | | | |
| | A9 | VREFN | A9 | VREFN | | | | | | | |
| | B1 | ddr_a5 | B1 | ddr_a5 | | | | | | | |
| | B2 | ddr_wen | B2 | ddr_wen | | | | | | | |
| | B3 | ddr_ba2 | B3 | ddr_ba2 | | | | | | | |
| | B4 | ENZ_KALDO_1P8V | B4 | ENZ_KALDO_1P8V | | | | | | | |
X3.A30 | X_PORZ = Global Reset-Signal | B5 | RTC_porz | B5 | RTC_porz | | | | | | | |
| | B9 | VREFP | B9 | VREFP | | | | | | | |
| | C1 | ddr_a9 | C1 | ddr_a9 | | | | | | | |
| | C2 | ddr_a4 | C2 | ddr_a4 | | | | | | | |
| | C3 | ddr_a3 | C3 | ddr_a3 | | | | | | | |
| | C4 | ddr_ba0 | C4 | ddr_ba0 | | | | | | | |
| | C6 | PMIC_POWER_EN | C6 | PMIC_POWER_EN | | | | | | | |
| | D1 | ddr_nck | D1 | ddr_nck | | | | | | | |
| | D2 | ddr_ck | D2 | ddr_ck | | | | | | | |
| | D3 | ddr_a15 | D3 | ddr_a15 | | | | | | | |
| | D4 | ddr_a8 | D4 | ddr_a8 | | | | | | | |
| | D5 | ddr_a6 | D5 | ddr_a6 | | | | | | | |
| | E1 | ddr_ba1 | E1 | ddr_ba1 | | | | | | | |
| | E2 | ddr_a7 | E2 | ddr_a7 | | | | | | | |
| | E3 | ddr_a12 | E3 | ddr_a12 | | | | | | | |
| | E4 | ddr_a2 | E4 | ddr_a2 | | | | | | | |
| | F1 | ddr_casn | F1 | ddr_casn | | | | | | | |
| | F2 | ddr_a11 | F2 | ddr_a11 | | | | | | | |
| | F3 | ddr_a0 | F3 | ddr_a0 | | | | | | | |
| | F4 | ddr_a10 | F4 | ddr_a10 | | | | | | | |
| | G1 | ddr_odt | G1 | ddr_odt | | | | | | | |
X3.B53 | X_MMC0_CLK | G17 | mmc0_clk | G17 | mmc0_clk | gpmc_a24_mux1 | uart3_ctsn_mux0 | uart2_rxd_mux2 | dcan1_tx_mux2 | pr1_pru0_pru_r30[12] | pr1_pru0_pru_r31[12] | gpio2[30] |
| | G2 | ddr_resetn | G2 | ddr_resetn | | | | | | | |
| | G3 | ddr_cke | G3 | ddr_cke | | | | | | | |
| | G4 | ddr_rasn | G4 | ddr_rasn | | | | | | | |
| | H1 | ddr_a1 | H1 | ddr_a1 | | | | | | | |
X1.A18 | X_RMII_REFCLK/_GPIO0_29 (wenn J5 = 1+2) | H18 | rmii1_refclk | H18 | rmii1_refclk | xdma_event_intr2_mux0 | spi1_cs0_mux1 | uart5_txd_mux0 | mcasp1_axr3_mux1 | mmc0_pow_mux0 | mcasp1_ahclkx_mux1 | gpio0[29] |
| | H2 | ddr_csn0 | H2 | ddr_csn0 | | | | | | | |
| | H3 | ddr_a13 | H3 | ddr_a13 | | | | | | | |
| | H4 | ddr_a14 | H4 | ddr_a14 | | | | | | | |
| | J1 | ddr_d8 | J1 | ddr_d8 | | | | | | | |
| | J2 | ddr_dqm1 | J2 | ddr_dqm1 | | | | | | | |
| | J3 | ddr_vtp | J3 | ddr_vtp | | | | | | | |
| | J4 | ddr_vref | J4 | ddr_vref | | | | | | | |
| | K1 | ddr_d9 | K1 | ddr_d9 | | | | | | | |
| | K2 | ddr_d10 | K2 | ddr_d10 | | | | | | | |
| | K3 | ddr_d11 | K3 | ddr_d11 | | | | | | | |
| | K4 | ddr_d12 | K4 | ddr_d12 | | | | | | | |
| | L1 | ddr_dqs1 | L1 | ddr_dqs1 | | | | | | | |
| | L2 | ddr_dqsn1 | L2 | ddr_dqsn1 | | | | | | | |
| | L3 | ddr_d13 | L3 | ddr_d13 | | | | | | | |
| | L4 | ddr_d14 | L4 | ddr_d14 | | | | | | | |
| | M1 | ddr_d15 | M1 | ddr_d15 | | | | | | | |
| | M2 | ddr_dqm0 | M2 | ddr_dqm0 | | | | | | | |
| | M3 | ddr_d0 | M3 | ddr_d0 | | | | | | | |
| | M4 | ddr_d1 | M4 | ddr_d1 | | | | | | | |
| | N1 | ddr_d2 | N1 | ddr_d2 | | | | | | | |
| | N2 | ddr_d3 | N2 | ddr_d3 | | | | | | | |
| | N3 | ddr_d4 | N3 | ddr_d4 | | | | | | | |
| | N4 | ddr_d5 | N4 | ddr_d5 | | | | | | | |
| | P1 | ddr_dqs0 | P1 | ddr_dqs0 | | | | | | | |
X3.B41 | X_USB0_VBUS | P15 | USB0_VBUS | P15 | USB0_VBUS | | | | | | | |
| | P2 | ddr_dqsn0 | P2 | ddr_dqsn0 | | | | | | | |
| | P3 | ddr_d6 | P3 | ddr_d6 | | | | | | | |
| | P4 | ddr_d7 | P4 | ddr_d7 | | | | | | | |
X1.B23 | X_GPMC_WAIT | T17 | gpmc_wait0 | T17 | gpmc_wait0 | gmii2_crs | gpmc_csn4 | rmii2_crs_dv | mmc1_sdcd_mux0 | pr1_mii1_col | uart4_rxd_mux2 | gpio0[30] |
X3.B22 | X_USB1_VBUS | T18 | USB1_VBUS | T18 | USB1_VBUS | | | | | | | |
| | U11 | OSC0_OUT | U11 | OSC0_OUT | | | | | | | |
X1.A41 | X_RGMII2_TCLK | U15 | gpmc_a6 | U15 | gpmc_a6_mux0 | gmii2_txclk | rgmii2_tclk | mmc2_dat4_mux0 | gpmc_a22_mux0 | pr1_mii1_rxd2 | eQEP1_index_mux1 | gpio1[22] |
| | V10 | OSC0_IN | V10 | OSC0_IN | | | | | | | |
X3.B46 | X_LCD_PCLK | V5 | lcd_pclk | V5 | lcd_pclk | gpmc_a10_mux1 | pr1_mii0_crs_mux1 | pr1_edio_data_in4 | pr1_edio_data_out4 | pr1_pru1_pru_r30[10] | pr1_pru1_pru_r31[10] | gpio2[24] |
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