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This hardware manual describes the PCL-069 System on Module, referred to as phyCORE®-i.MX 8M Mini, and the PBA-C-15, referred to as phyBOARD®-Polis. This manual also specifies the phyCORE-i.MX 8M Mini and phyBOARD-Polis' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Mini microcontrollers can be found in the i.MX 8M Mini Microcontroller Data Sheet/Reference Manual.
The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.
Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.
Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 8M Mini on the phyBOARD-Polis. Be aware that not all components need to be considered when designing your own carrier board.
As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 8M Mini is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased kinds of functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:
Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution, new ideas can be brought to market in the most timely and cost-efficient manner.
For more information go to:
http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html
The part numbering of the phyCORE has the following structure:
In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html
For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
Assembly Options include a choice of Controller, RAM (Size/Type), Size of NAND Flash, interfaces available, vanishing, temperature range, as well as other features. Please contact our sales team to get more information on the ordering options available. |
PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.
PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be unpacked, handled, or operated in environments in which sufficient precautionary measures have been taken with respect to ESD dangers. Only appropriately trained personnel such as qualified electricians, technicians, and engineers should handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m. |
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly with respect to the pin header row connectors, power connector, and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as the implementation of the products into target systems. |
With the purchase of a PHYTEC SOM / SBC you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.
Our general philosophy here is: We never discontinue a product as long as there is a demand for it.
Therefore, we have established a set of methods to fulfill our philosophy:
Avoidance strategies:
Change management in the rare event of an obsolete and non-replaceable part:
Change management in case of functional changes:
We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.
PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:
On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.
After finishing the Quickstart Guide, we recommend working through the Development Environment Guide. This will give you a comprehensive overview of the features and functions of both the SOM and carrier board. |
These manuals and more can be found in the download section of phyCORE-i.MX 8M Mini Product page.
This hardware manual describes the PCL-069 System on Module, referred to as phyCORE®-i.MX 8M Mini, and the PB-02820-xxxxx.Ax, referred to as phyBOARD®-Polis. The manual specifies the phyCORE-i.MX 8M Mini and phyBOARD-Polis' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Mini microcontrollers can be found in the i.MX 8M Mini Microcontroller Data Sheet/Reference Manual.
Due to part maintenance for our products (which are subject to continuous changes), we refrain from providing detailed, part-specific information within this manual. Please read the section Product Change Management and Information Regarding Parts Populated on the SOM / SBC within the Preface for more information. |
The BSP delivered with the phyCORE-i.MX 8M Mini includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at register level is not necessary in most cases. For this reason, this manual contains no detailed description of the controller's registers or information relevant to software development. Please refer to the NXP i.MX 8M Mini Reference Manual, if such information is needed to connect customer-designed applications. |
The conventions used in this manual are as follows:
Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.
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Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate any unfamiliar terms used in this document.
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The phyCORE‑i.MX 8M Mini belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.
Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 37 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.
phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.
The phyCORE‑i.MX 8M Mini is a sub-miniature (37 mm x 40 mm) soldered System on Module populated with the NXP® Semiconductor i.MX 8M Mini microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to a 1,27mm pitch BGA Ball. Each signal ball has an associated GND pin which ensures the GND reference for each signal. The ball packages are placed in lines. There is enough space between lines to ensure the possibility of easy routing out of the package. Signal balls for a high-speed signal like HDMI are placed on the outer lines, making it easy to route to the top layer of the carrier board. The SOM is designed to support carrier boards with as few as 6 layers to reduce PCB costs. For proper EMC characteristics, it is necessary to place the processor caps directly under the SOM. This required a hole in the carrier board.
The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Mini. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Mini.
The phyCORE‑i.MX 8M Mini offers the following features:
2 GB (up to 4 GB)
The maximum memory size listed as of the printing of this manual. |
) LPDDR4 RAM
1x 10/100/1000 MBit Ethernet interface (if Ethernet transceiver is mounted)
Please refer to the order options described in the Preface |
We recommend connecting all available VDD_3V3 input pins to the power supply system on a custom carrier board housing the phyCORE-i.MX 8M Mini and, at minimum, the matching number of GND pins neighboring the VDD_3V3 input pins. In addition, proper implementation of the phyCORE-i.MX 8M Mini module into a target application also requires connecting all GND pins. |
Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, the user must take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. |
All controller signals extend to BGA Signal Balls (1.27 mm) which allows the phyCORE‑i.MX 8M Mini to be soldered into any target application like a "big chip".
PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Mini Connector X1. This table contains a complete signal path for the phyCORE‑i.MX 8M Mini and the carrier board phyBOARD-Polis, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the pinout table.
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Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
It is good design practice to never rely on the SoC-internal pull resistors. |
It is recommended to handle unused signals according to the table below:
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The phyCORE‑i.MX 8M Mini operates off of a single power supply voltage. The following sections discuss the primary power pins on the phyCORE-i.MX 8M Mini Connector X1 in detail.
The phyCORE‑i.MX 8M Mini operates with a single primary voltage supply. Onboard switching and low dropout regulators generate the 2.5 V, 1.8 V, 1.2 V, 1.1 V, 0.9 V, and 0.8 V voltage rails required by the i.MX 8M Mini CPU and onboard components from the input voltage VDD_3V3.
For proper operation, the phyCORE‑i.MX 8M Mini must be supplied with a voltage source of 3.3 V +4.5 %-4 % with 2 A load at the VDD pins on the phyCORE-i.MX 8M Mini Connector X1.
In order to perform a full power cycle of the phyCORE-i.MX 8M Mini, including the SNVS domain of the PMIC and the CPU, the voltage input rail VDD_3V3 has to remain below 0,3 V for at least 600 ms.
It is recommended to choose a slightly higher value than 3.3 V for VDD_3V3 in order to account for series resistance of 3.3 V load switching components on the SoM. The PHYTEC phyBOARD-Polis for example supplies VDD_3V3 with 3.366 V ±3.5 %. |
VDD_3V3: X1 → A75, A76, A77, A78
Connect all VDD_3V3 input pins to your power supply and, at the very least, the matching number of GND pins.
Corresponding GND: X1 → B36, B37, B38, B39, B40, B41
Please refer to the section Pin Description for information on additional GND pins located at the phyCORE-i.MX 8M Mini Connector X1.
As a general design rule, PHYTEC recommends connecting all GND pins neighboring signals which are being used in the application circuitry. For maximum EMI performance, all GND pins should be connected to a solid ground plane. |
The phyCORE-i.MX 8M Mini provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The Powering Scheme figure presents a graphical depiction of the powering scheme. The PMIC supports many functions like on-chip RTC and different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Mini via the onboard I2C bus (I2C1) (I2C Interface). The I2C address of the PMIC is 0x08.
External voltages:
Internally generated voltages:
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The voltage level of the phyCORE’s logic circuitry is VDD_3V3_S (3.3 V) which is derived from the SOM main input voltage, VDD_3V3. In order to follow the mandatory power-up and power-down sequencing for the i.MX 8M Mini, external devices have to be supplied by the I/O supply voltage VDD_3V3_S which is brought out at pin E14 of the phyCORE-Connector. The use of VDD_3V3_S ensures that external components are only supplied when the supply voltages of the i.MX 8M Mini are stable.
The current draw for VDD_3V3_S must not exceed 500 mA. Consequently, this voltage should only be used as a reference or supply voltage for level shifters. VDD_3V3_S cannot be used to supply high-powered applications. If devices with higher power consumption are connected to the phyCORE‑i.MX 8M Mini, their supply voltage should be switched on and off by use of the X_PGOOD signal. This way, the power-up and power-down sequencing will be considered even if the devices are not supplied directly by VDD_3V3_S. |
If used to control or supply bus switches on the phyCORE side, VDD_3V3_S separates the supply voltages generated on the phyCORE‑i.MX 8M Mini and the supply voltages used on the carrier board/custom application. This way, voltages at the IO pins of the phyCORE-i.MX 8M Mini which are sourced from the supply voltage of peripheral devices attached to the SOM are avoided. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M Mini are supposed to be powered while the phyCORE‑i.MX 8M Mini is in suspend mode or turned off. The bus switches can be supplied by VDD_3V3_S on the phyCORE side, or the bus switches' output enabled to the SOM can be controlled by X_PGOOD to prevent these voltages from occurring. The use of level shifters supplied with VDD_3V3_S allows the signals to be converted according to the needs of the custom target hardware. Alternatively, signals can be connected to an open drain circuitry with a pull-up resistor attached to VDD_3V3_S. |
At pin A79 (Signal VBAT) of the phyCORE-i.MX 8M Mini, a secondary 3.3 V voltage source may be attached to the SOM. The PMIC (U3) will use this secondary source to generate NVCC_SNVS_1P8 in case VDD_3V3 falls below a value of approx. 2.8 V.
At pin A102 (Signal VRTC) of the phyCORE-i.MX 8M Mini, a secondary voltage source may be attached to the SOM in order to buffer the onboard RTC U12, while the SOM input voltage is not present. This manual describes only one of the available RTC active power states, which is used in conjunction with the phyBOARD-POLIS and the phyCORE-i.MX 8M Mini. The RTC RV-3028-C7 will enter its backup mode as soon as it detects the voltage level at Pin VRTC to be higher than the SOM input voltage VDD_3V3.
For further details on the functionalities of the RTC RV-3028-C7 please refer to Micro Crystal Switzerland Application Manual RV-3028-C7.
In its backup power state, the RTC will cease to communicate over I2C1 if the voltage level at the Pin VRTC is higher than the SOM input voltage VDD_3V3. In order to avoid unnecessary problems, the recommended voltage difference between VDD_3V3 and VRTC is approx. 300 mV. |
Pin C43 on the phyCORE-Connector is designated as an open-drain reset input with a pull-up resistor, that triggers a hard reset of the module. The external reset signal is connected to the enable signal of the voltage supervisor U41, which triggers a watchdog event in the PMIC resulting in a hard reset of the module. For debouncing purposes, the U41 delays the signal by 8,804 ms.
For PCB versions 1518.0, 1518.1a and 1518.2 additional precautions have to be taken regarding the undervoltage detection of the phyCORE-i.MX 8M Mini. X_nPOR_IN must be held on a logical low level, as long as VDD_3V3 is below 3.135 V. If this is not considered in the design of a baseboard, there is a small chance that the SoM could enter an unspecified mode of operation. PCB version 1518.3 and higher will not require this feature any longer, yet it is good engineering practice, to monitor all voltage rails at all times.
The PMIC reset output signal POR_B is made available at the phyCORE-Connector through a buffer as the open drain signal X_nPOR_OUT_OD. X_nPOR_OUT_OD is not connected to a pull-up resistor on the module. This leaves the user the freedom to choose the voltage domain used on the target hardware.
In case of a hard reset, regardless if it was triggered internally or externally, the PMIC holds the POR_B signal low until the module voltages are at stabilized levels. The POR_B signal is released approximately 11 ms after the last module voltage is correctly generated.
In order to perform a full power cycle of the phyCORE-i.MX 8M Mini, including the SNVS domain of the PMIC and the CPU, the voltage input rail VDD_3V3 has to remain below 0,3 V for at least 600 ms.
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Most features of the i.MX 8M Mini microcontroller are configured and/or programmed during the initialization routine. Essential boot features however are latched into i.MX 8M Mini registers from pre-configured pull-resistors following power-on reset (POR_B) de-assertion.
The latched-in information includes:
The internal ROM code is the first code executed during the initialization process of the i.MX 8M Mini after POR de-assertion. The ROM code detects the boot mode through pins X_BOOT_MODE0 and X_BOOT_MODE1, while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO pins (BOOT_CFGx[14:12]).
The i.MX 8M Mini boot mode is determined by the logical levels of the pins X_BOOT_MODE0 and X_BOOT_MODE1 approx. 31 µs after POR_B de-assertion. X_BOOT_MODE0 and X_BOOT_MODE1 are brought out at the phyCORE‑Connector pins C15 and C16. Possible settings and the resulting boot configuration of the i.MX 8M Mini are described in the following table:
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The BOOT_MODE[1:0] lines have 10 kΩ pull-up and pull-down resistors populated on the module. The default boot mode on the phyCORE-i.MX 8M Mini is set to internal boot mode, hence leaving the two pins unconnected will result in the unavailability of the remaining boot mode settings. The default boot device of phyCORE-i.MX 8M Mini is eMMC at SDIO3. Once in serial downloader boot, the ROM code polls the USB1 interface, initiates the download of the code into the internal RAM, and triggers its execution from there. In serial downloader boot mode the BOOT_CFG pins are ignored. Please refer to the NXP i.MX 8M Mini Reference Manual for more detailed information.
In fuse boot and internal boot mode, the ROM code finds the bootloader in permanent memories, such as eMMC or SD-Cards, and executes it. The boot device selection and the required interface configuration are accomplished with the help of the eFUSEs and/or the corresponding GPIO input.
In fuse boot and internal boot mode, the ROM code uses the BOOT_CFG pin states and eFUSEs to determine the boot device and its detailed configuration.
During development, it is advisable to set the Boot Source to “Internal boot” so that choosing and configuring the boot device using GPIO pin inputs is available. The BOOT_CFG pins are sampled shortly after POR de-assertion and, if the BT_FUSE_SEL fuse is not blown, override the values of the corresponding eFUSEs BOOT_CFGx[14:0].
The Boot Configuration Pins table lists the eFUSEs BOOT_CFGx[14:0] and the corresponding input pins. On the phyCORE‑i.MX 8M Mini, the BOOT_CFG GPIOs have 10 kΩ pull-up and pull-down resistors pre-installed to configure eFUSEs BOOT_CFGx[14:0] in accordance with the module features.
The specific boot configuration settings, set by the on-board configuration resistors, can be changed by modifying the resistors on the module or overwritten by connecting a configuration resistor (e.g. 1 kΩ) to the configuration signal. Choosing to not pull the boot configuration pins to a high or low level will lead to the configuration (other than the default configuration setting) being unavailable.
Furthermore, accidental pull resistances must be considered when designing base hardware for the phyCORE-i.MX 8M Mini. Any IC or passive component that forces a high or low level at one of the designated boot mode or boot configuration pins needs to be gated away during boot mode or boot configuration latch-in. A bus switch, buffer, or transistor circuit may yield the required results.
Please consider that any change of the default boot configuration can also influence other boot modes, which might result in faulty boot behavior. Please refer to the NXP i.MX 8M Mini Reference Manual for further information about the eFUSEs and the impact of the settings at the boot configuration pins.
The following table shows the phyCORE-i.MX 8M Mini default boot device configuration setting:
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The following table shows an excerpt from the complete boot configuration table in the NXP i.MX 8M Mini Reference Manual, edited to represent the phyCORE-i.MX 8M Mini's available boot configuration settings:
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The following table shows the properties of BOOT_CFG[14:0] during reset and during runtime and their location on the phyCORE-Connector, as well as their signal names.
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The i.MX 8M Nano uses a boot process different from the i.MX 8M Mini. Boot devices with fixed configuration may be selected through the use of 6 Boot Mode pins, 2 of which are shared with the i.MX 8M Mini. The phyCORE-i.MX 8M Nano is pre-configured with the default Boot Mode setting eMMC boot.
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The phyCORE‑i.MX 8M Mini provides four types of onboard memory:
One bank LPDDR4 RAM: 2 GB LPDDR4 RAM (up to 4 GB)
The maximum memory size listed is as of the printing of this manual. Please contact PHYTEC for more information about additional, or new module configurations available. |
The following sections detail each memory type used on the phyCORE‑i.MX 8M Mini.
The RAM memory of the phyCORE‑i.MX 8M Mini is comprised of one 32-bit wide bank with two 16-bit wide LPDDR4-RAM chips in one integrated circuit. The chips are connected to the DDR interface called the DDR Controller (DDRC) of the i.MX 8M Mini microcontroller.
Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Mini controller. Refer to the NXP i.MX 8M Mini Reference Manual for accessing and configuring these registers.
The Quad NOR flash memory at U7 is connected to the Flexible Serial Peripheral Interface A (FlexSPI A). The connected flash device uses the provided Chip Select 0 signal (QSPIA_SS0). The NOR flash device is powered by the 1.8 V supply voltage VDD_1V8. No further voltages are required to program the device.
As of the printing of this manual, these NOR flash devices generally have a life expectancy of at least 100,000 erase cycles per sector and a data retention rate of typically 20 years. Any parts that are footprint (TBGA-24 5x5) and functionally compatible may be used with the phyCORE-i.MX 8M Mini.
For more information about the NOR Flash, please refer to the NXP i.MX 8M Mini Reference Manual.
The managed NAND (eMMC) flash device is powered by the supply voltages VDD_1V8 (1.8 V) and VDD_3V3_S (3.3 V). No further voltages are required for programming the device. The eMMC memory is connected to the SDIO3 interface of the i.MX 8M Mini. Any parts that are footprint (BGA153) and functionally compatible may be used with the phyCORE-i.MX 8M Mini.
For more information about the eMMC, please refer to the NXP i.MX 8M Mini Reference Manual.
The phyCORE‑i.MX 8M Mini is populated with a 4 kB I2C
See the manufacturer’s datasheet for interfacing and operation. |
EEPROM at U13. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I2C port 1 of the i.MX 8M Mini. The control registers for I2C port 1 are mapped between addresses 0x021A 8000 and 0x021A BFFF. Please see the NXP i.MX 8M Mini Reference Manual for detailed information on the registers.
The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I2C address 0x51.
The Write Control (WC) signal of the EEPROM is permanently fixed to GND over resistor R106, so the EEPROM is not always write-protected.
The phyCORE‑i.MX 8M Mini provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to allow direct connection to external devices:
The following sections detail each of these serial interfaces.
The SDIO interfaces are part of the ultra Secured Digital Host Controller and can be used to connect external SD-Cards, eMMC, or any other device requiring an SDIO interface (examples include WiFI, I/O expansion). The phyCORE‑i.MX 8M Mini features two SDIO interfaces (4 and 8-Bit). On the phyCORE‑i.MX 8M Mini, the interface signals extend from the controller's first and second Ultra Secured Digital Host Controller (uSDHC1/uSDHC2) to the phyCORE-Connector.
uSDHC2 provides dedicated card-detect, write-protect and power enable signals. For uSDHC2 to function a pull-up resistor (eg. 10k) from X_SD2_PWR_EN to the SOM input voltage VDD_3V3 is required. This enables the uSDHC2 interface by powering the corresponding domain in the i.MX 8M Mini. This feature may be used to limit access to the CPU through an openly available SD-Card slot, or for similar purposes.
uSDHC1 card-detect and write-protect functions may be implemented by using GPIOs of the i.MX 8M Mini. Refer to the NXP i.MX 8M Mini Reference Manual. For more information about SD-Cards, please refer to the manufacturer's user manual.
The tables below show the locations of the various interface signals on the phyCORE-Connector. The Ultra Secure Digital Host Controller is fully compatible with SD/SDIO 3.0 (200MHz SDR signaling for up to 100 MB/s) and MMC 5.1 (HS400 DDR for up to 400 MB/s). uSDHC1 and uSDHC3 both provide 8-Bit interfaces, and uSDHC2 provides a 4-Bit interface. Refer to the NXP i.MX 8M Mini Reference Manual for more information.
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The phyCORE‑i.MX 8M Mini provides four high-speed universal asynchronous interfaces. Hardware flow control (RTS and CTS signals) may be implemented through the use of additional GPIO signals. See muxing options in NXP i.MX 8M Mini Reference Manual for more information. Location of the signals on the phyCORE-Connector:
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The phyCORE‑i.MX 8M Mini provides two high-speed USB OTG interfaces, which use the i.MX 8M Mini’s embedded High-Speed USB 2.0 PHY.
For the use of various USB functionalities, only an external USB Standard-A (for USB host), USB Standard-B (for USB devices), or USB Mini-AB (for USB OTG) connector is needed. The applicable interface signals (DN, DP, ID, and VBUS) are located on the phyCORE‑Connector X1. The locations of the USB OTG interface signals on the phyCORE-Connector X1 can be found in the tables below.
If overcurrent and power-enable signals are needed for the USB host interface, the functionality can be easily implemented through the use of GPIOs.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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Connection of the phyCORE‑i.MX 8M Mini to the World Wide Web or a local area network (LAN) is possible using the onboard GbE PHY at U4. It is connected to the RGMII interface of the i.MX 8M Mini. The PHY operates with a data transmission speed of 10, 100, or 1000 Mbit/s. Alternatively, the RGMII interface which is available on the phyCORE‑Connector can be used to connect an external PHY. In this case, the onboard GbE PHY (U4) must not be populated (see RGMII Interface).
With an Ethernet PHY mounted at U4, the phyCORE‑i.MX 8M Mini has been designed for use in 10/100/1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE-i.MX 8M Mini Connector X1.
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The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or a cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.
The Ethernet PHY is connected to the RGMII interface of the i.MX 8M Mini. Please refer to the NXP i.MX 8M Mini Reference Manual for more information about this interface.
In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, ETH0_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals.
Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.
The Ethernet PHY at U4 can be reset via software. The reset input of the Ethernet PHY is connected to the Power-On Reset (POR) signal of the module and to the GPIO RESET_ETHPHY of the i.MX 8M Mini.
In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Mini is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.
In order to use an external Ethernet PHY instead of the onboard GbE PHY at U8, the RGMII interface (ENET) of the i.MX 8M Mini is brought out at phyCORE-i.MX 8M Mini Connector X1.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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The GbE PHY (U4) must not be populated on the module if the RGMII interface is used. |
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The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI interfaces on the phyCORE‑i.MX 8M Mini Connector X1.
Each SPI interface provides one chip-select signal. The enhanced Configurable SPI (eCSPI) of the i.MX 8M Mini has three separate modules (eCSPI1, eCSPI2, and eCSPI3) which support data rates of up to 20 Mbit/s. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. The third SPI module can be made available through the i.MX 8M Mini pin muxing options. Refer to the NXP i.MX 8M Mini Reference Manual for more detailed information. All modules are master/slave configurable. The following tables list the SPI signals on the phyCORE-i.MX 8M Mini Connector X1.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Mini contains four identical, independent Multimaster fast-mode I2C modules. The interface of three modules is available at the phyCORE-Connector. The first I2C module (I2C1) connects to the onboard EEPROM at U13 (I2C EEPROM), the PMIC at U3 (Power Management IC), the Real-Time Clock at U12, and the MIPI to LVDS converter at U5 LVDS (FlatLink). The MIPI to LVDS converter connects to the I2C1 interface through the level shifter U22. The voltage domain in this part of the bus is 1,8 V.
To ensure the proper functioning of the I2C interface, external pull resistors matching the load at the interface must be connected. There are no pull-up resistors mounted on the module. For detailed information on the voltage levels for the pull-up resistors, please refer to the i.MX 8M Mini datasheet. |
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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The following tables list the I2C ports on the phyCORE-Connector, separated by interface:
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The first I2C module (I2C1) connects to the onboard EEPROM at U13 and the PMIC at U3. The following table shows the addresses of all I2C1 devices on the phyCORE-i.MX 8M Mini:
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The phyCORE-i.MX 8M Mini features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces: SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-i.MX 8M Mini Connector X1. All signals are part of the VDD_3V3_S voltage domain.
SAI1 provides 8-bit transmit and 8-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations. The tables below show the signal locations for each SAI interface.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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SAI2 provides 1-bit transmit and 1-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations.
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SAI3 provides 1-bit transmit and 1-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations.
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SAI5 provides 4-bit receive functionality with receive and master clock output. Frame synchronization is available for receive operations.
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The 1-lane PCI Express interface of the phyCORE‑i.MX 8M Mini provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interface is fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specification. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented via the use of GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Polis) for a circuit example. The table below show the signal location for the PCIe interface.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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The following table lists all pins not used by any of the other interfaces described explicitly in this manual and which, therefore, can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Mini. In addition, most pins directly routed to the phyCORE-i.MX M Mini Connector X1 can be configured as GPIO due to the multiplexing functionality of the i.MX 8M Mini.
For more details on the possible GPIO settings, see the NXP i.MX 8M Mini Reference Manual.
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The phyCORE‑i.MX 8M Mini is equipped with a JTAG interface for downloading program code into the external flash, internal controller RAM, or for any debugging programs that are executed. Location of the JTAG pins on the phyCORE-i.MX 8M Mini Connector X1:
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In the industrial market, LVDS is the default display with the best long-time availability. MIPI is normally used for the consumer market. For this reason, PHYTEC has added a MIPI to LVDS converter as part of the SOM design. This allows an LVDS display to be used in industrial applications. Alternatively, phyCORE-i.MX 8M MINI can be ordered without the converter and a jumper in its place so that a MIPI display can be used.
It is not possible to use both an LVDS and MIPI display at the same time. Only one type of display can be used at any given time. |
The LVDS interface of the phyCORE-i.MX 8M Mini, using an optional MIPI to LVDS converter, is converted from the i.MX 8M Mini’s MIPI-DSI2 interface. The converter supports resolutions of up to 1920x1200 (WUXGA) at 60 frames per second with 24 bpp and reduced blanking. It is also suitable for resolutions of 1366x768 with 60 frames per second and 1280x800 at 60 frames per second, both 18 and 24 bpp. The LVDS interface is available only when U5 is mounted. Please refer to the Texas Instruments SN65DSI83 datasheet for more information.
Location of the LVDS signals on the phyCORE-i.MX 8M Mini Connector:
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The i.MX 8M Mini’s MIPI-DSI2 interface provides resolutions of up to 1920x1080 at 60 frames per second. It uses four data channels and one clock channel. The MIPI-DSI2 interface is only available if the MIPI to LVDS converter U5 is not mounted. The interface provides a maximum bit rate of 1,5 Gbit/s.
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The phyCORE-i.MX 8M Mini features a MIPI CSI-2 camera interface. It is routed directly to phyCORE-i.MX 8M Mini Connector X1. The interface provides a maximum bit rate of 1,5 Gbit/s. It uses four data channels and one clock channel. All signals, including control signals and an I2C interface, to use the camera interfaces, according to PHYTEC's phyCAM‑S standard, are available at the phyCORE‑i.MX 8M Mini Connector.
The i.MX 8M Mini microcontroller is equipped with one MIPI camera interface. The following table shows the location of all MIPI CSI-2 interface signals on the phyCORE-Connector X1:
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The phyCORE-i.MX 8M Mini features a SPDIF interface. It is routed directly to phyCORE-i.MX 8M Mini Connector X1.
Existing issues may be solved by referring to the following chapters in NXP Mask Set Errata for Mask 0N87W, Rev. 1, 09/2021:
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The i.MX 8M Mini on the phyBOARD‑Polis is able to scale the clock frequency and voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as Dynamic Voltage and Frequency Scaling (DVFS).
The i.MX 8M Mini BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a minimum/maximum frequency as well as the applicable voltage and a governor that regulates these values depending on the system load. Depending on the i.MX 8M Mini variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M Mini BSP Manual.
Due to changes in functionality and design that are currently being developed, there are several values that cannot be determined in time for the release of this manual. All values with "TBD (To Be Determined)" are currently being evaluated. These values will be added to future manual editions. |
The module’s profile is a maximum of 10 mm thick, with a maximal component height of 3.0 mm on the bottom (connector) side of the PCB and approximately 5.0 mm on the top (microcontroller) side. The board itself is approximately 1.4 mm thick.
To facilitate the integration of the phyCORE‑i.MX 8M Mini into your design, the footprint of the phyCORE‑i.MX 8M Mini can be downloaded (see Integrating the phyCORE-i.MX 8M Mini). |
Additional Specifications:
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These specifications describe the standard configuration of the phyCORE‑i.MX 8M Mini as of the printing of this manual.
In order to illustrate the power consumption of the phyCORE-i.MX 8M Mini in various realistic load scenarios, multiple measurements were conducted. It is important to note, that these measurements are a sole depiction of the specific stresses, asserted to the SOM through the specified software applications. The given results may be utilized to dimension a power supply for the phyCORE-i.MX 8M Mini on custom hardware. Especially custom software may yield different results in power consumption compared to the values posted in the table below. It is vital that power consumption of the phyCORE-i.MX 8M Mini is evaluated when it is intended to be used with custom software.
The power consumption of the phyCORE-i.MX 8M Mini was measured at the 3.3 V SOM input voltage rail. The results below do not account for a possible current draw through the switched 3.3 V voltage rail VDD_3V3_S. The SOM is capable of drawing the measured current continuously. In case the ambient temperature varies greatly from the underlying test conditions for this measurement, a difference in power consumption may be observed.
In the applicable datasheet, the manufacturer of the i.MX 8M Mini CPU defines maximum current ratings for each voltage rail, which are designated as a guideline during the dimensioning of the on-module power supply and the resulting voltage rails. The mentioned absolute current ratings were considered in the design process of the phyCORE-i.MX 8M Mini's power infrastructure, yet does not represent realistic use cases for the SOM.
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For further information and assistance regarding your application's power consumption, please contact PHYTEC sales. |
The i.MX 8M Mini offers various low-power modes. For further, more detailed information, on how to activate and utilize the different low-power modes please refer to the PHYTEC phyCORE-i.MX 8M Mini BSP Manual and NXP i.MX 8M Mini Reference Manual. The phyCORE-i.MX 8M Mini supports the following low-power modes:
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The right temperature grade of the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below). If necessary, a heat spreader can be used for temperature compensation. |
The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts, such as the ones described within this manual, are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.
However, the above-mentioned parts are available at different temperature qualification levels by the producers. We offer our SOMs in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.
The Product Temperature Grades table describes these grades in detail. These grades describe a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.
In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:
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The phyCORE i.MX 8M Mini uses Fused Tin Grid Array (FTGA) to mount to a carrier board (for example, phyBOARD-Polis). FTGA provides several advantages:
For more information about FTGA soldering, please refer to the PHYTEC FTGA Soldering Guide (LAN-095e.A1 i.MX 8M Mini Fused Tin Grid Array (FTGA) Soldering Information).
Apart from this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Mini into customer applications.
Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. As a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.
The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework stations, or other desoldering methods is strongly recommended. Follow the instructions carefully for whatever method of removal is used.
The manufacturer guarantee is voided if any modifications to the module are performed, regardless of their nature. |
The phyBOARD‑Polis for phyCORE-i.MX 8M Mini is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M Mini microcontroller. Due to numerous standard interfaces, the phyBOARD‑Polis can serve as the bedrock for any application. At the core of the phyBOARD‑Polis is the PCL-069/phyCORE-i.MX 8M Mini System On Module (SOM) containing the processor, DRAM, eMMC, power regulation, supervision, transceivers, and other core functions required to support the i.MX 8M Mini processor. Surrounding the SOM is the PB-02820-xxxxx.Ax/phyBOARD‑Polis carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.
The PCL-069 System On Module connects to the phyBOARD‑Polis carrier board using a Ball Grid Array (BGA). The PCL-069 SOM is soldered directly onto the phyBOARD‑Polis using PHYTEC's Direct Solder Connect technology. This solution offers an ultra-low-cost Single Board Computer for the i.MX 8M Mini processor, while maintaining most of the advantages of the SOM concept.
phyCORE carrier boards are designed and tested to be used in:
PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy.
This modular development platform concept includes the following components:
The carrier board can also serve as a reference design for the development of custom target hardware in which the phyCORE SOM is deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.
The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time to market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") that are continuously being refined and updated.
Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Polis, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.
For any necessary detail adjustment, extension connectors are available which allow a wide variety of functions to be added.
For further information, please contact PHYTEC sales. |
The phyBOARD‑Polis i.MX 8M Mini supports the following features:
1x USB 2.0 host interface brought out to a USB Standard-A connector
There is no protective circuit for the USB interfaces brought out at the Mini PCI Express or the expansion connector. |
The phyBOARD‑Polis features many different interfaces and is equipped with the components listed in table Connectors and Pin Headers. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Polis Components (Top) and phyBOARD-Polis Components (Bottom) highlight the location of each component for easy identification.
This is a list of all available connectors on the phyBOARD-Polis.
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Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, the user must take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. |
The phyBOARD-Polis is populated with one LED, which is user-programmable. phyBOARD-Polis Components (Top) shows the location of the LED.
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The phyBOARD-Polis is populated with 3 switches. The tables below show their function:
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Additionally, S1 is a 5-port dip switch bar populated for several functions:
The phyBOARD-Polis comes pre-configured with several solder jumpers (J). The jumpers enable the flexible configuration of a limited number of features for development purposes.
Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Contact our sales team if you need jumper configurations different from the default configuration. |
This section provides a more detailed look at the phyBOARD‑Polis components. Each subsection details a particular connector/interface for configuring that interface.
Where possible, we also provide any useful information regarding design considerations for components. This can be used if you plan to design your own carrier board. |
Do not change modules or jumper settings while the phyBOARD‑Polis is supplied with power! |
The phyBOARD-Polis is available with one power supply connector, a 2-pole Combicon Phoenix connector suitable for a single supply voltage (X33).
The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Polis, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board. The power input is protected against overcurrent with a fuse (F1). A suppressor diode (D36) protects against polarity reversal. The pin assignment of the power input connector X33:
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It is recommended to route high current rails, like the SOM supply voltage, as planes to keep series resistance at a minimum. The same thing should be applied to ground paths. For more information, see phyCORE-i.MX 8M Mini Power Consumption.
The phyCORE-i.MX 8M Mini features 4 UART interfaces. On the phyBOARD-Polis, TTL level UART2 is available at the A/V connector (X18) and TTL level UART4 is available at the expansion connector (X8). The availability of UART3 at the expansion connector depends on the state of the debug USB port and the configuration of switch S1 (Multi-port Switch) If a USB device is connected to the debug USB port (USB Debug), UART3 will only be available for the FTDI U66. The following is a detailed description of UART states and conditions:
Further information on the switch S1 can be found in the section Multi-port Switch. Further information on the expansion connector X8 can be found in the section Expansion Connector. The following table shows the signal mapping of the RS-232 and RS-485 level signals at connector X9:
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When designing a custom carrier board, remember the TTL level is 3.3 V. Route signals as single-ended 50 Ohm lines.
The phyBOARD‑Polis is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and ACTIVITY (yellow) indications are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.
The following table shows the pin assignment of the Ethernet0 connector X1:
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The data lanes should be routed with a differential impedance of 100 Ohm and kept as short as possible. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a suitable resistor.
The phyBOARD-Polis provides one USB 2.0 and one USB OTG interface.
USB1 is accessible at the USB Micro-AB connector X2 and is configured as USB OTG. USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles with each other. This interface is compliant with USB revision 2.0. USB2 is accessible at the Standard-A connector X5 and is configured as a USB host.
The following tables show the pin assignments of the USB OTG and USB 2.0 interface:
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The data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.
The phyBOARD-Polis offers a USB debug interface, that is accessible via the USB micro-AB connector X30. When a USB device is plugged into X30, UART3 will automatically be routed to the UART to USB converter U87. The following table shows the pin configuration of the debug USB micro-AB connector X30:
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The UART data signals to the UART to USB converter should be routed as singled-ended signals with an impedance of 50 Ohm and kept as short as possible. The USB data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.
The phyBOARD‑Polis provides a standard microSDHC card slot at X4 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like SD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.
DIP switch S1 provides a toggle between default and SD-Card boot. In order to boot from SD-Card, S1 (pads 1-12) must be switched ON (refer to Multi-port Switch for further information).
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Series resistors in data and clock signals should be placed as close as possible to the signal source. For I/O signals this means two resistors in one electric net are recommended. The voltage of the SD2 signal lanes is NVCC_SD2 and can switch between 1.8 V and 3.3 V. The supply voltage of the SD-Card remains 3.3 V and should not be connected to NCVV_SD2. All signals should be routed as 50 Ohm single-ended lines.
The 1-lane PCI Express interface of the phyBOARD‑Polis provides PCIe Gen. 2.0 functionality, which supports 5 Gbit/s operations. The interface is fully backward compatible with the Gen. 1.1, 2.5 Gbit/s specifications. Various control signals are implemented with GPIOs. The pin assignment of the Mini PCI Express connector is shown in the following table:
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100nF AC-Coupling capacitors are placed close to output pins of the i.MX 8M Mini on the PCL-069 in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm.
The phyCORE-i.MX 8M Mini on the phyBOARD-Polis offers one interface to connect to digital cameras with the MIPI CSI-2 interface. The signals of the Camera Serial Interface (CSI) are available as a multi-lane LVDS camera interface together with an I2C interface to allow for a direct connection of appropriate camera modules. On the phyBOARD-Polis, the CMOS Camera Interface is brought out as a phyCAM-M camera interface at connector X10. Information on the phyCAM-M standard and other possibilities can be found in the phyCAM manual: https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-748e_10.pdf.
Pin assignment of the phyCAM-M MIPI CSI-2 connector X10:
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The CAN with Flexible Data-Rate (CAN FD) is an updated extension of the original CAN protocol. This enables extra data bytes and flexible bit rates. In general, the CAN FD offers 3 benefits to regular CAN:
Pin assignment of the CAN FD Connector X7:
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The Audio/Video (A/V) connectors X16 and X18 provide an easy way to add typical A/V functions and features to the phyBOARD‑Polis. Standard interfaces such as parallel display, I2S, and I2C as well as different supply voltages are available at the two 2 mm pitch dual inline sockets.
The A/V connector is intended for use with phyBOARD Expansion Boards
Please find additional information on phyBOARD Expansion Boards in the corresponding application guide (L-793e). |
and to add specific audio/video connectivity with custom expansion boards. A/V connector X16 makes all data and clock signals for display connectivity available. X18 provides signals for audio and touch screen connectivity as well as an I2C bus and additional control signals.
Pin assignments for A/V connectors X16 and X18:
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All signals should be routed as short as possible and as 50 Ohm single-ended lines.
The phyBOARD-Polis offers a 2x9 socket as a voice array connector with UART, I2C, and I2S functionality. The following table shows the pin assignment of the voice array connector X38:
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All signals should be routed as short as possible and as 50 Ohm single-ended lines.
The expansion connector X8 provides an easy way to add other functions and features to the phyBOARD‑Polis. Standard interfaces such as USB, SPDIF, JTAG, UART, SPI, and I2C as well as different supply voltages and some GPIOs are available at the female expansion connector. The expansion connector is intended for use with phyBOARD Expansion Boards and to add specific functions with custom expansion boards. Information on the expansion boards available for the expansion connector can be found in the Application Guide for phyBOARD Expansion Boards (L-793e).
Pin assignment of the expansion connector X8:
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All signals should be routed as short as possible and as 50 Ohm single-ended lines.
The I2C interfaces of the i.MX 8M Mini are available at different connectors on the phyBOARD‑Polis. The following table provides a list of the connectors and pins with I2C connectivity:
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The phyBOARD-Polis is equipped with a Trusted Platform Module (TPM). The TPM is a chip developed, produced, tested, and certified according to the TCG specification that enhances the board with additional security functions. These security functions include the generation and secure storage (in the hardware) of keys for the authentication and identification of communication participants (SSH, server, cloud, etc.) and data, which can also be encrypted.
The TPM requires either an SPI or I2C interface, depending on the mounted module. The TPM is connected to the SOM through the following interfaces:
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For more information about your security needs, contact a PHYTEC salesperson. |
The phyBOARD-Polis is equipped with a Wireless WLAN and Bluetooth Transceiver Module that is capable of providing WLAN and Bluetooth functionality. The module requires a UART with handshake capability and a 4-bit SDIO interface. The module is connected to the SOM through the following interfaces:
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The phyBOARD-Polis provides one multicolor (RGB) LED (D11). The table below shows the signals that control colors:
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All signals should be routed as short as possible and as 50 Ohm single-ended lines.
The phyBOARD‑Polis features a multi-port switch with six individually switchable ports. This switch controls the SOM boot mode, SOM boot configuration, UART functionality, and USB configuration when i.MX 8M NANO is mounted on the carrier board. The figures below show a visual representation of each S1 switch setting:
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All signals should be routed as short as possible and as 50 Ohm single-ended lines.
The phyBOARD‑Polis is equipped with a system reset button at S2. Pressing this button will toggle the X_nRESET_IN pin (C43) of the phyCORE-i.MX 8M Mini low, causing the module to reset with a complete power cycle. For more information regarding a manual reset, refer to Reset.
The phyBOARD-Polis is equipped with an ON/OFF button at S3. For more information on the ON/OFF switch, refer to the i.XM 8M Mini Reference Manual.
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