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在设备树中 设备树中的LCD液晶屏修改方法/LCD display timings in device tree
并口 / RGB
接并口屏幕需要参考imx6 datasheet中的以下章节
另外我们的设备树(PD16.1.0)默认未开启 DRDY/DV or DE Data Enable信号。
需要修改 imx6qdl-phytec-mira-peb-av-02.dtsi 文件
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi index 95e450c..66662d1 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira-peb-av-02.dtsi @@ -151,7 +151,7 @@ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b080 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x1b0b0 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
LVDS时钟切换
imx6自带有两路LVDS输出。
imx6的lvds模块可以有两个时钟输入,默认是低频率范围,无法达到37MHz以上。
在dts文件如 imx6q-phytec-mira-rdk-nand.dts 中添加下面的内容,可以切换到高速时钟。
&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; };
双通道LVDS
请参考:
&ldb { fsl,dual-channel; status = "okay"; lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; display-timings { native-mode = <&timing0>; timing0: hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; hback-porch = <220>; hfront-porch = <40>; vback-porch = <21>; vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; }; }; }; };
其中lvds的时钟频率是clock-frequency的一半,比如上面这个例子中,是32.5MHz。
如果这里的时钟频率超过56M,也要像之前那样配置LVDS的时钟。
fsl, dual-channel 的说明:https://github.com/torvalds/linux/blob/df0cc57e/Documentation/devicetree/bindings/display/imx/ldb.txt#L40
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